CPUMBState::@res_addr field is used as u32 since commit
cfeea807e5a ("target-microblaze: Tighten up TCGv_i32 vs
TCGv type usage"). Convert it as such, bumping the migration
version. Use the RES_ADDR_NONE definition when appropriate.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
target/microblaze/cpu.h | 2 +-
target/microblaze/machine.c | 6 +++---
target/microblaze/translate.c | 17 +++++++++--------
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3ce28b302fe..14b107876a4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -259,7 +259,7 @@ struct CPUArchState {
/* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation
*/
- target_ulong res_addr;
+ uint32_t res_addr;
uint32_t res_val;
/* Internal flags. */
diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c
index a4cf38dc891..48efa546d39 100644
--- a/target/microblaze/machine.c
+++ b/target/microblaze/machine.c
@@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = {
VMSTATE_UINT32(iflags, CPUMBState),
VMSTATE_UINT32(res_val, CPUMBState),
- VMSTATE_UINTTL(res_addr, CPUMBState),
+ VMSTATE_UINT32(res_addr, CPUMBState),
VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
@@ -87,8 +87,8 @@ static const VMStateField vmstate_env_fields[] = {
static const VMStateDescription vmstate_env = {
.name = "env",
- .version_id = 0,
- .minimum_version_id = 0,
+ .version_id = 1,
+ .minimum_version_id = 1,
.fields = vmstate_env_fields,
};
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ff33e64a710..04fbd4fe17f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -55,7 +55,7 @@ static TCGv_i32 cpu_imm;
static TCGv_i32 cpu_bvalue;
static TCGv_i32 cpu_btarget;
static TCGv_i32 cpu_iflags;
-static TCGv cpu_res_addr;
+static TCGv_i32 cpu_res_addr;
static TCGv_i32 cpu_res_val;
/* This is the state at translation time. */
@@ -857,7 +857,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
mo_endian(dc) | MO_UL);
- tcg_gen_mov_tl(cpu_res_addr, addr);
+ tcg_gen_mov_i32(cpu_res_addr, addr);
if (arg->rd) {
tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
@@ -1024,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* branch, but we know we can use the equal version in the global.
* In either case, addr is no longer needed.
*/
- tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
+ tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
/*
* Compare the value loaded during lwx with current contents of
@@ -1052,7 +1052,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* Prevent the saved address from working again without another ldx.
* Akin to the pseudocode setting reservation = 0.
*/
- tcg_gen_movi_tl(cpu_res_addr, -1);
+ tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
return true;
}
@@ -1173,7 +1173,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
}
tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP);
- tcg_gen_movi_tl(cpu_res_addr, -1);
+ tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
dc->base.is_jmp = DISAS_EXIT;
return true;
@@ -1194,7 +1194,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br
*arg)
if (arg->rd) {
tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
}
- tcg_gen_movi_tl(cpu_res_addr, -1);
+ tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
#ifdef CONFIG_USER_ONLY
switch (imm) {
@@ -1885,6 +1885,7 @@ void mb_tcg_init(void)
tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
}
- cpu_res_addr =
- tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr),
"res_addr");
+ cpu_res_addr = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUMBState, res_addr),
+ "res_addr");
}
