On Mon, 15 Sept 2025 at 09:59, Clément Chigot <[email protected]> wrote: > > From: Frederic Konrad <[email protected]> > > This wires a second GIC for the Cortex-R5, all the IRQs are split when there > is an RPU instanciated. > > Signed-off-by: Clément Chigot <[email protected]> > > --- > > Originally, this patch was member of a wider series. Other patches have > been merged since thus submit it back as a standalone patch. > https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg02328.html
Note that I am assuming that one of the Xilinx folks will review this patch. thanks -- PMM
