On Wed, Sep 24, 2025 at 7:21 PM Djordje Todorovic <[email protected]> wrote: > > Add mips.ccmov defined by Xmipscmov. > > Signed-off-by: Chao-ying Fu <[email protected]> > Signed-off-by: Djordje Todorovic <[email protected]> > Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 3 +++ > target/riscv/cpu_cfg.h | 5 ++++ > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/insn_trans/trans_xmips.c.inc | 32 +++++++++++++++++++++++ > target/riscv/meson.build | 1 + > target/riscv/translate.c | 3 +++ > target/riscv/xmips.decode | 11 ++++++++ > 7 files changed, 56 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc > create mode 100644 target/riscv/xmips.decode > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1a1ea7fe9a..77fbf67776 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -247,6 +247,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b), > ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), > + ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > @@ -1379,6 +1380,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), > MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), > MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), > + MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), > > { }, > }; > @@ -3293,6 +3295,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.pmp = true, > .cfg.ext_zba = true, > .cfg.ext_zbb = true, > + .cfg.ext_xmipscmov = true, > .cfg.marchid = 0x8000000000000201, > .cfg.mvendorid = MIPS_VENDOR_ID, > #ifndef CONFIG_USER_ONLY > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index aa28dc8d7e..2db471ad17 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -36,6 +36,11 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg > __attribute__((__unus > return true; > } > > +static inline bool has_xmips_p(const RISCVCPUConfig *cfg) > +{ > + return cfg->ext_xmipscmov; > +} > + > static inline bool has_xthead_p(const RISCVCPUConfig *cfg) > { > return cfg->ext_xtheadba || cfg->ext_xtheadbb || > diff --git a/target/riscv/cpu_cfg_fields.h.inc > b/target/riscv/cpu_cfg_fields.h.inc > index e2d116f0df..a290303ee7 100644 > --- a/target/riscv/cpu_cfg_fields.h.inc > +++ b/target/riscv/cpu_cfg_fields.h.inc > @@ -147,6 +147,7 @@ BOOL_FIELD(ext_xtheadmemidx) > BOOL_FIELD(ext_xtheadmempair) > BOOL_FIELD(ext_xtheadsync) > BOOL_FIELD(ext_XVentanaCondOps) > +BOOL_FIELD(ext_xmipscmov) > > BOOL_FIELD(mmu) > BOOL_FIELD(pmp) > diff --git a/target/riscv/insn_trans/trans_xmips.c.inc > b/target/riscv/insn_trans/trans_xmips.c.inc > new file mode 100644 > index 0000000000..045034ae32 > --- /dev/null > +++ b/target/riscv/insn_trans/trans_xmips.c.inc > @@ -0,0 +1,32 @@ > +/* > + * RISC-V translation routines for the MIPS extensions (xmips*). > + * > + * Copyright (c) 2025 MIPS > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + * > + * Reference: MIPS P8700 instructions > + * (https://mips.com/products/hardware/p8700/) > + */ > + > +#define REQUIRE_XMIPSCMOV(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xmipscmov) { \ > + return false; \ > + } \ > +} while (0) > + > +static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) > +{ > + REQUIRE_XMIPSCMOV(ctx); > + > + TCGv zero, source1, source2, source3; > + zero = tcg_constant_tl(0); > + source1 = get_gpr(ctx, a->rs1, EXT_NONE); > + source2 = get_gpr(ctx, a->rs2, EXT_NONE); > + source3 = get_gpr(ctx, a->rs3, EXT_NONE); > + > + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd], > + source2, zero, source1, source3); > + > + return true; > +} > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > index fbb6c8fb45..26cd11ec00 100644 > --- a/target/riscv/meson.build > +++ b/target/riscv/meson.build > @@ -4,6 +4,7 @@ gen = [ > decodetree.process('insn32.decode', extra_args: > '--static-decode=decode_insn32'), > decodetree.process('xthead.decode', extra_args: > '--static-decode=decode_xthead'), > decodetree.process('XVentanaCondOps.decode', extra_args: > '--static-decode=decode_XVentanaCodeOps'), > + decodetree.process('xmips.decode', extra_args: > '--static-decode=decode_xmips'), > ] > > riscv_ss = ss.source_set() > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 9ddef2d6e2..66d31b67d3 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1194,8 +1194,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > #include "insn_trans/trans_svinval.c.inc" > #include "insn_trans/trans_rvbf16.c.inc" > #include "decode-xthead.c.inc" > +#include "decode-xmips.c.inc" > #include "insn_trans/trans_xthead.c.inc" > #include "insn_trans/trans_xventanacondops.c.inc" > +#include "insn_trans/trans_xmips.c.inc" > > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > @@ -1211,6 +1213,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > > const RISCVDecoder decoder_table[] = { > { always_true_p, decode_insn32 }, > + { has_xmips_p, decode_xmips}, > { has_xthead_p, decode_xthead}, > { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, > }; > diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode > new file mode 100644 > index 0000000000..fadcb78470 > --- /dev/null > +++ b/target/riscv/xmips.decode > @@ -0,0 +1,11 @@ > +# > +# RISC-V translation routines for the MIPS extension > +# > +# Copyright (c) 2025 MIPS > +# > +# SPDX-License-Identifier: GPL-2.0-or-later > +# > +# Reference: MIPS P8700 instructions > +# (https://mips.com/products/hardware/p8700/) > + > +ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 > -- > 2.34.1 >
