On Fri, Oct 3, 2025 at 8:45 PM Djordje Todorovic
<[email protected]> wrote:
>
> Add a new function, so we can change reset vector from platforms
> during runtime.
>
> Signed-off-by: Chao-ying Fu <[email protected]>
> Signed-off-by: Djordje Todorovic <[email protected]>
> Reviewed-by: Daniel Henrique Barboza <[email protected]>
> ---
> target/riscv/cpu.c | 15 +++++++++++++++
> target/riscv/cpu.h | 4 ++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d055ddf462..d42cf9d70e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -73,6 +73,21 @@ bool riscv_cpu_option_set(const char *optname)
> return g_hash_table_contains(general_user_opts, optname);
> }
>
> +#ifndef CONFIG_USER_ONLY
> +/* This is used in runtime only. */
> +void cpu_set_exception_base(int vp_index, target_ulong address)
> +{
> + CPUState *cpu_state = qemu_get_cpu(vp_index);
We usually use `CPUState *cs` in QEMU
> + if (cpu_state == NULL) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "cpu_set_exception_base: invalid vp_index: %u",
> + vp_index);
> + }
> + RISCVCPU *vp = RISCV_CPU(cpu_state);
This should be `RISCVCPU *cpu` and should be defined at the top of the function
Otherwise
Reviewed-by: Alistair Francis <[email protected]>
Alistair
> + vp->env.resetvec = address;
> +}
> +#endif
> +
> static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig
> *src)
> {
> #define BOOL_FIELD(x) dest->x |= src->x;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4a862da615..34751bd414 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -672,6 +672,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> +#ifndef CONFIG_USER_ONLY
> +void cpu_set_exception_base(int vp_index, target_ulong address);
> +#endif
> +
> FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> FIELD(TB_FLAGS, FS, 3, 2)
> /* Vector flags */
> --
> 2.34.1
