Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/tlb-insns.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index bf8f007869..f7510a1208 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -536,6 +536,17 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
}
+static void tlbi_aa64_ipas2e1is_write128(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ CPUState *cs = env_cpu(env);
+ int mask = ipas2e1_tlbmask(env, vallo);
+ uint64_t pageaddr = sextract64(valhi << 12, 0, 56);
+
+ tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+}
+
static const ARMCPRegInfo tlbi_not_v7_cp_reginfo[] = {
/*
* MMU TLB control. Note that the wildcarding means we cover not just
@@ -719,12 +730,16 @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] = {
.writefn = tlbi_aa64_vae1_write },
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_ipas2e1is_write },
+ .access = PL2_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_ipas2e1is_write,
+ .write128fn = tlbi_aa64_ipas2e1is_write128 },
{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_ipas2e1is_write },
+ .access = PL2_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_ipas2e1is_write,
+ .write128fn = tlbi_aa64_ipas2e1is_write128 },
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
--
2.43.0
