Hi, Shameer On Mon, 29 Sept 2025 at 21:39, Shameer Kolothum <[email protected]> wrote: > > Hi, > > Changes from RFCv3: > > -Removed RFC tag as we have the user-creatable SMMUv3 sereis now applied[0] > -Addressed feedback from RFCv3. Thanks to all!(I believe I have addressed > all comments, apologies if I missed any) > -Removed dependency on “at least one cold-plugged vfio-pci device.” The > accelerated SMMUv3 features are now initialized based on QEMU SMMUv3 > defaults, and each time a device is attached, the host SMMUv3 info is > retrieved and features are cross-checked. > -Includes IORT RMR support to enable MSI doorbell address translation. > Thanks to Eric, this is based on his earlier attempt on DSM #5 and > IORT RMR support. > -Added optional properties (like ATS, RIL, etc.) for the user to override > the default QEMU SMMUv3 features. > -Deferred batched invalidation of commands for now. This series supports > basic single in-order command issuing to the host. Batched support will > be added as a follow up series. > -Includes synthesizing PASID capability for the assigned vfio-pci device. > Thanks to Yi’s effort, this is based on his out-of-tree patches. > -Added a migration blocker for now. Plan is to enable migration support > later. > -Has dependency(patches: 4/5/8)on Zhenzhong's pass-through support series[1] > > PATCH organization: > 1–20: Enables accelerated SMMUv3 with features based on default QEMU SMMUv3, > including IORT RMR based MSI support. > 21–23: Adds options for specifying RIL, ATS, and OAS features. > 24–27: Adds PASID support, including VFIO changes. > > Tests: > Performed basic sanity tests on an NVIDIA GRACE platform with GPU device > assignments. A CUDA test application was used to verify the SVA use case. > Further tests are always welcome. > > Eg: Qemu Cmd line: > > qemu-system-aarch64 -machine virt,gic-version=3,highmem-mmio-size=2T \ > -cpu host -smp cpus=4 -m size=16G,slots=2,maxmem=66G -nographic \ > -bios QEMU_EFI.fd -object iommufd,id=iommufd0 -enable-kvm \ > -object memory-backend-ram,size=8G,id=m0 \ > -object memory-backend-ram,size=8G,id=m1 \ > -numa node,memdev=m0,cpus=0-3,nodeid=0 -numa node,memdev=m1,nodeid=1 \ > -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 -numa > node,nodeid=5 \ > -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 -numa > node,nodeid=9 \ > -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0 \ > -device > arm-smmuv3,primary-bus=pcie.1,id=smmuv3.0,accel=on,ats=on,ril=off,pasid=on,oas=48 > \ > -device > pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,pref64-reserve=512G,id=dev0 > \ > -device > vfio-pci,host=0019:06:00.0,rombar=0,id=dev0,iommufd=iommufd0,bus=pcie.port1 \ > -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=2 \ > ... > -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=9 \ > -device pxb-pcie,id=pcie.2,bus_nr=8,bus=pcie.0 \ > -device > arm-smmuv3,primary-bus=pcie.2,id=smmuv3.1,accel=on,ats=on,ril=off,pasid=on \ > -device pcie-root-port,id=pcie.port2,bus=pcie.2,chassis=2,pref64-reserve=512G > \ > -device > vfio-pci,host=0018:06:00.0,rombar=0,id=dev1,iommufd=iommufd0,bus=pcie.port2 \ > -device virtio-blk-device,drive=fs \ > -drive file=image.qcow2,index=0,media=disk,format=qcow2,if=none,id=fs \ > -net none \ > -nographic > > A complete branch can be found here, > https://github.com/shamiali2008/qemu-master smmuv3-accel-v4
I have tested this series with stall enabled. https://github.com/Linaro/qemu/pull/new/10.1.50-wip Tested-by: Zhangfei Gao <[email protected]> By the way, the stall feature requires some additional patches, including page fault handling. Shall we handle that after this series? Thanks
