and update formatting in logs.
Signed-off-by: Anton Johansson <[email protected]>
---
target/riscv/cpu.h | 2 +-
target/riscv/machine.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8c8d34f3ac..32e30a36ac 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -323,7 +323,7 @@ struct CPUArchState {
uint64_t mtvec;
uint64_t mepc;
- target_ulong mcause;
+ uint64_t mcause;
uint64_t mtval; /* since: priv-1.10.0 */
uint64_t mctrctl;
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index f42be027e3..438c44dbb0 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -442,7 +442,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT64(env.scause, RISCVCPU),
VMSTATE_UINT64(env.mtvec, RISCVCPU),
VMSTATE_UINT64(env.mepc, RISCVCPU),
- VMSTATE_UINTTL(env.mcause, RISCVCPU),
+ VMSTATE_UINT64(env.mcause, RISCVCPU),
VMSTATE_UINT64(env.mtval, RISCVCPU),
VMSTATE_UINTTL(env.miselect, RISCVCPU),
VMSTATE_UINTTL(env.siselect, RISCVCPU),
--
2.51.0
