On Wed, Oct 15, 2025 at 6:34 AM Anton Johansson via <[email protected]> wrote: > > Fix these fields to 64 bits as they cannot be made smaller. Also make > sure stores to these fields from TCG are 64 bits in size to avoid > incorrect values on big endian hosts. > > Signed-off-by: Anton Johansson <[email protected]> > Reviewed-by: Pierrick Bouvier <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 4 ++-- > target/riscv/machine.c | 2 +- > target/riscv/translate.c | 6 ++++-- > target/riscv/insn_trans/trans_privileged.c.inc | 2 +- > 4 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f2378d0b67..8c93030b1c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -233,8 +233,8 @@ struct CPUArchState { > uint8_t frm; > float_status fp_status; > > - target_ulong badaddr; > - target_ulong bins; > + uint64_t badaddr; > + uint64_t bins; > > target_ulong guest_phys_fault_addr; > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 07995fb303..b047321073 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -437,7 +437,7 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINT64(env.load_res, RISCVCPU), > VMSTATE_UINT64(env.load_val, RISCVCPU), > VMSTATE_UINT8(env.frm, RISCVCPU), > - VMSTATE_UINTTL(env.badaddr, RISCVCPU), > + VMSTATE_UINT64(env.badaddr, RISCVCPU), > VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), > VMSTATE_UINTTL(env.priv_ver, RISCVCPU), > VMSTATE_UINTTL(env.vext_ver, RISCVCPU), > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 6b84d0c384..2770c06413 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -253,7 +253,7 @@ static void generate_exception(DisasContext *ctx, > RISCVException excp) > > static void gen_exception_illegal(DisasContext *ctx) > { > - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, > + tcg_gen_st_i64(tcg_constant_i64(ctx->opcode), tcg_env, > offsetof(CPURISCVState, bins)); > if (ctx->virt_inst_excp) { > generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); > @@ -264,7 +264,9 @@ static void gen_exception_illegal(DisasContext *ctx) > > static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) > { > - tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); > + TCGv_i64 ext = tcg_temp_new_i64(); > + tcg_gen_extu_tl_i64(ext, target); > + tcg_gen_st_i64(ext, tcg_env, offsetof(CPURISCVState, badaddr)); > generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); > } > > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc > b/target/riscv/insn_trans/trans_privileged.c.inc > index 8a62b4cfcd..a8eaccef67 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -68,7 +68,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) > if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { > generate_exception(ctx, RISCV_EXCP_SEMIHOST); > } else { > - tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, > + tcg_gen_st_i64(tcg_constant_i64(ebreak_addr), tcg_env, > offsetof(CPURISCVState, badaddr)); > generate_exception(ctx, RISCV_EXCP_BREAKPOINT); > } > -- > 2.51.0 > >
