On Tue, 14 Oct 2025 at 21:19, Richard Henderson <[email protected]> wrote: > > Signed-off-by: Richard Henderson <[email protected]>
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode > index 01b1b3e38b..c76757ed01 100644 > --- a/target/arm/tcg/a64.decode > +++ b/target/arm/tcg/a64.decode > @@ -302,9 +302,15 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 > 011 11111 > # same instruction as far as QEMU is concerned. > # NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have > # to hand-decode it. > -SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 > -SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 > -SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 > +&sys l op0 op1 op2 crn crm rt > +SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0=1 > +SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0=2 > +SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0=3 > + > +# MRRS, MSRR > +SYS128 1101 0101 01 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0=2 > +SYS128 1101 0101 01 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0=3 > +SYSP 1101 0101 01 0 01 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0=1 > l=0 I think we should decode the L bit here, and allow handle_sys() to deliver the UNDEF, same as we do for 64-bit SYS. I know that currently there are no 128-bit "system instruction with result" insns, but there also weren't any 64-bit "system instruction with result" insns until FEAT_GCS added GCSPOPM and GCSSS2... Otherwise Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
