Expose WG CPU extensions (Smwg, Sswg, Smwgd) and WG CPU configs (mwid, mwidlist).
Signed-off-by: Jim Shu <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 32a9f8a6a4..b8704e7e88 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1380,6 +1380,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), + /* RISC-V WorldGuard v0.4 */ + MULTI_EXT_CFG_BOOL("x-smwg", ext_smwg, false), + MULTI_EXT_CFG_BOOL("x-smwgd", ext_smwgd, false), + MULTI_EXT_CFG_BOOL("x-sswg", ext_sswg, false), + { }, }; @@ -2648,6 +2653,9 @@ static const Property riscv_cpu_properties[] = { * it with -x and default to 'false'. */ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), + + DEFINE_PROP_UINT32("x-mwid", RISCVCPU, cfg.mwid, UINT32_MAX), + DEFINE_PROP_UINT32("x-mwidlist", RISCVCPU, cfg.mwidlist, UINT32_MAX), }; static const gchar *riscv_gdb_arch_name(CPUState *cs) -- 2.43.0
