>-----Original Message----- >From: Cédric Le Goater <[email protected]> >Subject: Re: [PATCH v7 12/23] intel_iommu: Add some macros and inline >functions > >On 10/24/25 10:43, Zhenzhong Duan wrote: >> Add some macros and inline functions that will be used by following >> patch. >> >> This patch also make a cleanup to change macro >VTD_SM_PASID_ENTRY_DID >> and VTD_SM_PASID_ENTRY_FSPM to use extract64() just like what smmu >does, >> because they are either used in following patches or used indirectly by >> new introduced inline functions. But we doesn't aim to change the huge >> amount of bit mask style macro definitions in this patch, that should be >> in a separate patch. >> >> Suggested-by: Eric Auger <[email protected]> >> Signed-off-by: Zhenzhong Duan <[email protected]> >> Reviewed-by: Yi Liu <[email protected]> >> --- >> hw/i386/intel_iommu_internal.h | 8 +++++-- >> hw/i386/intel_iommu.c | 38 >+++++++++++++++++++++++++++------- >> 2 files changed, 37 insertions(+), 9 deletions(-) >> >> diff --git a/hw/i386/intel_iommu_internal.h >b/hw/i386/intel_iommu_internal.h >> index 09edba81e2..df80af839d 100644 >> --- a/hw/i386/intel_iommu_internal.h >> +++ b/hw/i386/intel_iommu_internal.h >> @@ -642,10 +642,14 @@ typedef struct VTDPASIDCacheInfo { >> #define VTD_SM_PASID_ENTRY_PT (4ULL << 6) >> >> #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted >guest-address-width */ >> -#define VTD_SM_PASID_ENTRY_DID(val) ((val) & >VTD_DOMAIN_ID_MASK) >> +#define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) >> >> -#define VTD_SM_PASID_ENTRY_FSPM 3ULL >> #define VTD_SM_PASID_ENTRY_FSPTPTR (~0xfffULL) >> +#define VTD_SM_PASID_ENTRY_SRE_BIT(x) extract64((x)->val[2], 0, 1) >> +/* 00: 4-level paging, 01: 5-level paging, 10-11: Reserved */ >> +#define VTD_SM_PASID_ENTRY_FSPM(x) extract64((x)->val[2], 2, >2) >> +#define VTD_SM_PASID_ENTRY_WPE_BIT(x) extract64((x)->val[2], 4, >1) >> +#define VTD_SM_PASID_ENTRY_EAFE_BIT(x) extract64((x)->val[2], 7, 1) >> >> /* First Stage Paging Structure */ >> /* Masks for First Stage Paging Entry */ >> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c >> index 56abbb991d..871e6aad19 100644 >> --- a/hw/i386/intel_iommu.c >> +++ b/hw/i386/intel_iommu.c >> @@ -52,8 +52,7 @@ >> >> /* pe operations */ >> #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & >VTD_SM_PASID_ENTRY_PGTT) >> -#define VTD_PE_GET_FS_LEVEL(pe) \ >> - (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FSPM)) >> +#define VTD_PE_GET_FS_LEVEL(pe) (VTD_SM_PASID_ENTRY_FSPM(pe) + >4) >> #define VTD_PE_GET_SS_LEVEL(pe) \ >> (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) >> >> @@ -837,6 +836,31 @@ static inline bool >vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe) >> } >> } >> >> +static inline dma_addr_t vtd_pe_get_fspt_base(VTDPASIDEntry *pe) >> +{ >> + return pe->val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; >> +} >> + >> +/* >> + * First stage IOVA address width: 48 bits for 4-level paging(FSPM=00) >> + * 57 bits for 5-level >paging(FSPM=01) >> + */ >> +static inline uint32_t vtd_pe_get_fs_aw(VTDPASIDEntry *pe) >> +{ >> + return 48 + VTD_SM_PASID_ENTRY_FSPM(pe) * 9; > > >Can't we use VTD_HOST_AW_48BIT here ?
Will do. Thanks Zhenzhong
