Extended feature register 2 (EFR2) exposes newer IOMMU features such as NUM_INT_REMAP_SUP. Set MMIO offset 0x01A0 and ACPI table entry to EFR2.
Signed-off-by: Sairaj Kodilkar <[email protected]> --- hw/i386/acpi-build.c | 4 +++- hw/i386/amd_iommu-stub.c | 5 +++++ hw/i386/amd_iommu.c | 20 +++++++++++++++++--- hw/i386/amd_iommu.h | 4 ++++ 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9446a9f862ca..1d4fd064e9a5 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1873,7 +1873,9 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, amdvi_extended_feature_register(s), 8); /* EFR Register Image 2 */ - build_append_int_noprefix(table_data, 0, 8); + build_append_int_noprefix(table_data, + amdvi_extended_feature_register2(s), + 8); /* IVHD entries as found above */ g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); diff --git a/hw/i386/amd_iommu-stub.c b/hw/i386/amd_iommu-stub.c index d62a3732e60f..39b1afc0c751 100644 --- a/hw/i386/amd_iommu-stub.c +++ b/hw/i386/amd_iommu-stub.c @@ -24,3 +24,8 @@ uint64_t amdvi_extended_feature_register(AMDVIState *s) { return AMDVI_DEFAULT_EXT_FEATURES; } + +uint64_t amdvi_extended_feature_register2(AMDVIState *s) +{ + return AMDVI_DEFAULT_EXT_FEATURES2; +} diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 8b146f4d33d2..3221bf5a0303 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -114,6 +114,11 @@ uint64_t amdvi_extended_feature_register(AMDVIState *s) return feature; } +uint64_t amdvi_extended_feature_register2(AMDVIState *s) +{ + return AMDVI_DEFAULT_EXT_FEATURES2; +} + /* configure MMIO registers at startup/reset */ static void amdvi_set_quad(AMDVIState *s, hwaddr addr, uint64_t val, uint64_t romask, uint64_t w1cmask) @@ -123,6 +128,16 @@ static void amdvi_set_quad(AMDVIState *s, hwaddr addr, uint64_t val, stq_le_p(&s->w1cmask[addr], w1cmask); } +static void amdvi_refresh_efrs(struct AMDVIState *s) +{ + amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES, + amdvi_extended_feature_register(s), + 0xffffffffffffffef, 0); + amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES2, + amdvi_extended_feature_register2(s), + 0xffffffffffffffff, 0); +} + static uint16_t amdvi_readw(AMDVIState *s, hwaddr addr) { return lduw_le_p(&s->mmior[addr]); @@ -2307,6 +2322,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &iommu_as[devfn]->as; } + static bool amdvi_set_iommu_device(PCIBus *bus, void *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { @@ -2434,9 +2450,7 @@ static void amdvi_init(AMDVIState *s) /* reset MMIO */ memset(s->mmior, 0, AMDVI_MMIO_SIZE); - amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES, - amdvi_extended_feature_register(s), - 0xffffffffffffffef, 0); + amdvi_refresh_efrs(s); amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, 0x98, 0x67); } diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index e6f6902fe06d..c8eaf229b50e 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -57,6 +57,7 @@ #define AMDVI_MMIO_EXCL_BASE 0x0020 #define AMDVI_MMIO_EXCL_LIMIT 0x0028 #define AMDVI_MMIO_EXT_FEATURES 0x0030 +#define AMDVI_MMIO_EXT_FEATURES2 0x01A0 #define AMDVI_MMIO_COMMAND_HEAD 0x2000 #define AMDVI_MMIO_COMMAND_TAIL 0x2008 #define AMDVI_MMIO_EVENT_HEAD 0x2010 @@ -229,6 +230,8 @@ AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) +#define AMDVI_DEFAULT_EXT_FEATURES2 (0) + /* capabilities header */ #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ @@ -433,5 +436,6 @@ struct AMDVIState { }; uint64_t amdvi_extended_feature_register(AMDVIState *s); +uint64_t amdvi_extended_feature_register2(AMDVIState *s); #endif -- 2.34.1
