From: Anton Johansson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Anton Johansson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
hw/riscv/riscv-iommu.c | 6 ++++--
hw/riscv/riscv_hart.c | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index b33c7fe3259..f8656ec04b1 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -26,6 +26,8 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/timer.h"
+#include "qemu/target-info.h"
+#include "qemu/bitops.h"
#include "cpu_bits.h"
#include "riscv-iommu.h"
@@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s,
RISCVIOMMUContext *ctx,
const uint64_t va_mask = (1ULL << va_len) - 1;
if (pass == S_STAGE && va_len > 32) {
- target_ulong mask, masked_msbs;
+ uint64_t mask, masked_msbs;
- mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
+ mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
masked_msbs = (addr >> (va_len - 1)) & mask;
if (masked_msbs != 0 && masked_msbs != mask) {
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 4d51a93dd52..33cbc9873e6 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -94,7 +94,7 @@ static bool csr_qtest_callback(CharFrontend *chr, gchar
**words)
g_assert(rc == 0);
csr_call(words[1], cpu, csr, &val);
- qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
+ qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
return true;
}
--
2.51.0
