On Tue, Oct 28, 2025 at 4:23 AM Anton Johansson via <[email protected]> wrote: > > [m|s|vs]iselect are defined in version 20250508 of the privileged > specification to be XLEN in size, however QEMU only ever uses at most > 16 bits of these fields, so fix them to 16. Update relevant function > arguments. > > Signed-off-by: Anton Johansson <[email protected]> > Reviewed-by: Pierrick Bouvier <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 6 +++--- > target/riscv/csr.c | 32 ++++++++++++++++---------------- > target/riscv/machine.c | 6 +++--- > 3 files changed, 22 insertions(+), 22 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5f051796f4..b35851cf4f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -343,8 +343,8 @@ struct CPUArchState { > uint8_t siprio[64]; > > /* AIA CSRs */ > - target_ulong miselect; > - target_ulong siselect; > + uint16_t miselect; > + uint16_t siselect; > uint64_t mvien; > uint64_t mvip; > > @@ -390,7 +390,7 @@ struct CPUArchState { > uint64_t vsatp; > > /* AIA VS-mode CSRs */ > - target_ulong vsiselect; > + uint16_t vsiselect; > > uint64_t mtval2; > uint64_t mtinst; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5ba1fe4168..ebdb955869 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2405,7 +2405,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env, > int csrno, > target_ulong *val, target_ulong new_val, > target_ulong wr_mask) > { > - target_ulong *iselect; > + uint16_t *iselect; > int ret; > > ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > @@ -2448,18 +2448,18 @@ static RISCVException rmw_xiselect(CPURISCVState > *env, int csrno, > return RISCV_EXCP_NONE; > } > > -static bool xiselect_aia_range(target_ulong isel) > +static bool xiselect_aia_range(uint16_t isel) > { > return (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) || > (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST); > } > > -static bool xiselect_cd_range(target_ulong isel) > +static bool xiselect_cd_range(uint16_t isel) > { > return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST); > } > > -static bool xiselect_ctr_range(int csrno, target_ulong isel) > +static bool xiselect_ctr_range(int csrno, uint16_t isel) > { > /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */ > return CTR_ENTRIES_FIRST <= isel && isel <= CTR_ENTRIES_LAST && > @@ -2467,7 +2467,7 @@ static bool xiselect_ctr_range(int csrno, target_ulong > isel) > } > > static int rmw_iprio(target_ulong xlen, > - target_ulong iselect, uint8_t *iprio, > + uint16_t iselect, uint8_t *iprio, > target_ulong *val, target_ulong new_val, > target_ulong wr_mask, int ext_irq_no) > { > @@ -2511,7 +2511,7 @@ static int rmw_iprio(target_ulong xlen, > return 0; > } > > -static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val, > +static int rmw_ctrsource(CPURISCVState *env, uint16_t isel, target_ulong > *val, > target_ulong new_val, target_ulong wr_mask) > { > /* > @@ -2550,7 +2550,7 @@ static int rmw_ctrsource(CPURISCVState *env, int isel, > target_ulong *val, > return 0; > } > > -static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val, > +static int rmw_ctrtarget(CPURISCVState *env, uint16_t isel, target_ulong > *val, > target_ulong new_val, target_ulong wr_mask) > { > /* > @@ -2589,7 +2589,7 @@ static int rmw_ctrtarget(CPURISCVState *env, int isel, > target_ulong *val, > return 0; > } > > -static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val, > +static int rmw_ctrdata(CPURISCVState *env, uint16_t isel, target_ulong *val, > target_ulong new_val, target_ulong wr_mask) > { > /* > @@ -2630,7 +2630,7 @@ static int rmw_ctrdata(CPURISCVState *env, int isel, > target_ulong *val, > } > > static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, > - target_ulong isel, target_ulong *val, > + uint16_t isel, target_ulong *val, > target_ulong new_val, target_ulong wr_mask) > { > bool virt = false, isel_reserved = false; > @@ -2710,12 +2710,12 @@ done: > } > > static int rmw_xireg_cd(CPURISCVState *env, int csrno, > - target_ulong isel, target_ulong *val, > + uint16_t isel, target_ulong *val, > target_ulong new_val, target_ulong wr_mask) > { > int ret = -EINVAL; > - int ctr_index = isel - ISELECT_CD_FIRST; > - int isel_hpm_start = ISELECT_CD_FIRST + 3; > + uint16_t ctr_index = isel - ISELECT_CD_FIRST; > + uint16_t isel_hpm_start = ISELECT_CD_FIRST + 3; > > if (!riscv_cpu_cfg(env)->ext_smcdeleg || > !riscv_cpu_cfg(env)->ext_ssccfg) { > ret = RISCV_EXCP_ILLEGAL_INST; > @@ -2782,7 +2782,7 @@ done: > } > > static int rmw_xireg_ctr(CPURISCVState *env, int csrno, > - target_ulong isel, target_ulong *val, > + uint16_t isel, target_ulong *val, > target_ulong new_val, target_ulong wr_mask) > { > if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) { > @@ -2810,7 +2810,7 @@ static int rmw_xireg_ctr(CPURISCVState *env, int csrno, > * extension using csrind should be implemented here. > */ > static int rmw_xireg_csrind(CPURISCVState *env, int csrno, > - target_ulong isel, target_ulong *val, > + uint16_t isel, target_ulong *val, > target_ulong new_val, target_ulong wr_mask) > { > bool virt = csrno == CSR_VSIREG ? true : false; > @@ -2840,7 +2840,7 @@ static int rmw_xiregi(CPURISCVState *env, int csrno, > target_ulong *val, > target_ulong new_val, target_ulong wr_mask) > { > int ret = -EINVAL; > - target_ulong isel; > + uint16_t isel; > > ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > if (ret != RISCV_EXCP_NONE) { > @@ -2871,7 +2871,7 @@ static RISCVException rmw_xireg(CPURISCVState *env, int > csrno, > target_ulong wr_mask) > { > int ret = -EINVAL; > - target_ulong isel; > + uint16_t isel; > > ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > if (ret != RISCV_EXCP_NONE) { > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 8a8f5be8d6..376075b2bd 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper = { > VMSTATE_UINT64(env.vscause, RISCVCPU), > VMSTATE_UINT64(env.vstval, RISCVCPU), > VMSTATE_UINT64(env.vsatp, RISCVCPU), > - VMSTATE_UINTTL(env.vsiselect, RISCVCPU), > + VMSTATE_UINT16(env.vsiselect, RISCVCPU), > VMSTATE_UINT64(env.vsie, RISCVCPU), > > VMSTATE_UINT64(env.mtval2, RISCVCPU), > @@ -467,8 +467,8 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINT64(env.mepc, RISCVCPU), > VMSTATE_UINT64(env.mcause, RISCVCPU), > VMSTATE_UINT64(env.mtval, RISCVCPU), > - VMSTATE_UINTTL(env.miselect, RISCVCPU), > - VMSTATE_UINTTL(env.siselect, RISCVCPU), > + VMSTATE_UINT16(env.miselect, RISCVCPU), > + VMSTATE_UINT16(env.siselect, RISCVCPU), > VMSTATE_UINT32(env.scounteren, RISCVCPU), > VMSTATE_UINT32(env.mcounteren, RISCVCPU), > VMSTATE_UINT32(env.scountinhibit, RISCVCPU), > -- > 2.51.0 > >
