Implicit writes to USR are only to specific fields of USR to indicate side effects (e.g., saturation overflow, floating point status). In these cases, we don't force a packet commit. This will allow more packets to be short-circuited (avoid writing the results to temporaries).
Signed-off-by: Taylor Simpson <[email protected]> --- target/hexagon/translate.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 8fce219c0d..3da01c2b5e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -272,12 +272,7 @@ static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum) { uint16_t opcode = ctx->insn->opcode; if (GET_ATTRIB(opcode, attrib)) { - /* - * USR is used to set overflow and FP exceptions, - * so treat it as conditional - */ - bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) || - rnum == HEX_REG_USR; + bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC); /* LC0/LC1 is conditionally written by endloop instructions */ if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) && @@ -300,8 +295,6 @@ static void mark_implicit_reg_writes(DisasContext *ctx) mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); - mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); } static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum) @@ -351,11 +344,6 @@ static bool need_commit(DisasContext *ctx) } } - /* Floating point instructions are hard-coded to use new_value */ - if (check_for_attrib(pkt, A_FPOP)) { - return true; - } - if (ctx->read_after_write || ctx->has_hvx_overlap) { return true; } -- 2.43.0
