On Mon, Oct 27, 2025 at 8:12 PM Michael Levit <[email protected]> wrote: > > From: Michael <[email protected]> > > Introduce NEORV32 RV32 CPU type under target/riscv, wire NEORV32 vendor ID, > and add a vendor CSR (CSR_MXISA) guarded by mvendorid match, plus meson glue.
Looks good. There are a bunch of whitespace errors though, can you run your patches through checkpatch.pl Alistair > > Signed-off-by: Michael Levit <[email protected]> > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 75f4e43408..a39bf853cc 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -57,6 +57,8 @@ > #define TYPE_RISCV_CPU_XIANGSHAN_NANHU > RISCV_CPU_TYPE_NAME("xiangshan-nanhu") > #define TYPE_RISCV_CPU_XIANGSHAN_KMH > RISCV_CPU_TYPE_NAME("xiangshan-kunminghu") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > +#define TYPE_RISCV_CPU_NEORV32 RISCV_CPU_TYPE_NAME("neorv32") > + > > OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 73d4280d7c..7bcf93c66c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -245,6 +245,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, > ext_xtheadmempair), > ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), > ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, > ext_XVentanaCondOps), > + ISA_EXT_DATA_ENTRY(xneorv32xisa,PRIV_VERSION_1_10_0,ext_xneorv32xisa), > > { }, > }; > @@ -1366,6 +1367,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), > MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), > MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), > + MULTI_EXT_CFG_BOOL("xneorv32xisa", ext_xneorv32xisa, false), > > { }, > }; > @@ -3032,6 +3034,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.pmp_regions = 8 > ), > > + > #if defined(TARGET_RISCV32) || \ > (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) > DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, > @@ -3075,6 +3078,21 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .misa_mxl_max = MXL_RV32, > .misa_ext = RVE > ), > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_NEORV32, TYPE_RISCV_VENDOR_CPU, > + .misa_mxl_max = MXL_RV32, > + .misa_ext = RVI | RVM | RVA | RVC | RVU, > + .priv_spec = PRIV_VERSION_1_10_0, > + > + .cfg.max_satp_mode = VM_1_10_MBARE, > + .cfg.ext_zifencei = true, > + .cfg.ext_zicsr = true, > + .cfg.pmp = true, > + .cfg.pmp_regions = 16, > + .cfg.mvendorid = NEORV32_VENDOR_ID, > +#ifndef CONFIG_USER_ONLY > + .custom_csrs = neorv32_csr_list > +#endif > + ), > #endif > > #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 36e7f10037..6a9918a25a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -985,5 +985,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool > is_32_bit); > /* In th_csr.c */ > extern const RISCVCSR th_csr_list[]; > > +/* Implemented in neorv32_csr.c */ > +extern const RISCVCSR neorv32_csr_list[]; > + > const char *priv_spec_to_str(int priv_version); > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index aa28dc8d7e..9ad38506e4 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -64,5 +64,6 @@ MATERIALISE_EXT_PREDICATE(xtheadmemidx) > MATERIALISE_EXT_PREDICATE(xtheadmempair) > MATERIALISE_EXT_PREDICATE(xtheadsync) > MATERIALISE_EXT_PREDICATE(XVentanaCondOps) > +MATERIALISE_EXT_PREDICATE(xneorv32xisa) > > #endif > > diff --git a/target/riscv/cpu_cfg_fields.h.inc > b/target/riscv/cpu_cfg_fields.h.inc > index a154ecdc79..b84e1bd287 100644 > --- a/target/riscv/cpu_cfg_fields.h.inc > +++ b/target/riscv/cpu_cfg_fields.h.inc > @@ -147,6 +147,7 @@ BOOL_FIELD(ext_xtheadmemidx) > BOOL_FIELD(ext_xtheadmempair) > BOOL_FIELD(ext_xtheadsync) > BOOL_FIELD(ext_XVentanaCondOps) > +BOOL_FIELD(ext_xneorv32xisa) > > BOOL_FIELD(mmu) > BOOL_FIELD(pmp) > > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h > index 96b6b9c2cb..66a8f30b81 100644 > --- a/target/riscv/cpu_vendorid.h > +++ b/target/riscv/cpu_vendorid.h > @@ -7,4 +7,6 @@ > #define VEYRON_V1_MIMPID 0x111 > #define VEYRON_V1_MVENDORID 0x61f > > +#define NEORV32_VENDOR_ID 0xF0000001 > + > #endif /* TARGET_RISCV_CPU_VENDORID_H */ > > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > index fdefe88ccd..44e706ad3f 100644 > --- a/target/riscv/meson.build > +++ b/target/riscv/meson.build > @@ -40,6 +40,7 @@ riscv_system_ss.add(files( > 'th_csr.c', > 'time_helper.c', > 'riscv-qmp-cmds.c', > + 'neorv32_csr.c', > )) > > subdir('tcg') > > diff --git a/target/riscv/neorv32_csr.c b/target/riscv/neorv32_csr.c > new file mode 100644 > index 0000000000..0cb8663436 > --- /dev/null > +++ b/target/riscv/neorv32_csr.c > @@ -0,0 +1,54 @@ > +/* > + * Neorv32-specific CSR. > + * > + * Copyright (c) 2025 Michael Levit > + * > + * Author: > + * Michael Levit <[email protected]> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along > with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "cpu.h" > +#include "cpu_vendorid.h" > + > +#define CSR_MXISA (0xfc0) > + > +static RISCVException smode(CPURISCVState *env, int csrno) > +{ > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_neorv32_xisa(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + /* We don't support any extension for now on QEMU */ > + *val = 0x00; > + return RISCV_EXCP_NONE; > +} > + > +static bool test_neorv32_mvendorid(RISCVCPU *cpu) > +{ > + return cpu->cfg.mvendorid == NEORV32_VENDOR_ID; > +} > + > +const RISCVCSR neorv32_csr_list[] = { > + { > + .csrno = CSR_MXISA, > + .insertion_test = test_neorv32_mvendorid, > + .csr_ops = { "neorv32.xisa", smode, read_neorv32_xisa } > + }, > + { } > +}; > + > -- > 2.51.1 >
