From: Richard Henderson <[email protected]> Currently an unpredictable movw such as
movw pc, 0x123 results in the tinycode and_i32 $0x123,$0x123,$0xfffffffc mov_i32 pc,$0x123 exit_tb $0x0 which is clearly a bug: writing to a constant is incorrect and discards the result of the mask. Fix this by always doing an and_i32 and trusting the optimizer to turn this into a simple move when the mask is zero. Signed-off-by: Anton Johansson <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Tested-by: Gustavo Romero <[email protected]> Reviewed-by: <[email protected]> Message-id: [email protected] [rth: Avoid an extra temp and extra move.] Signed-off-by: Richard Henderson <[email protected]> [PMM: commit message tweak] Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 5f64fed2202..63735d97898 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -303,20 +303,23 @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) marked as dead. */ void store_reg(DisasContext *s, int reg, TCGv_i32 var) { + uint32_t mask = 0; + if (reg == 15) { - /* In Thumb mode, we must ignore bit 0. + /* + * In Thumb mode, we must ignore bit 0. * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0] * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0]. * We choose to ignore [1:0] in ARM mode for all architecture versions. */ - tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); + mask = s->thumb ? 1 : 3; s->base.is_jmp = DISAS_JUMP; s->pc_save = -1; } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) { /* For M-profile SP bits [1:0] are always zero */ - tcg_gen_andi_i32(var, var, ~3); + mask = 3; } - tcg_gen_mov_i32(cpu_R[reg], var); + tcg_gen_andi_i32(cpu_R[reg], var, ~mask); } /* -- 2.43.0
