According to Volume 1 Manual 7.4.8, certain exceptions require setting CSR_BADV, but the code does not match.this patch correct it. and the exception PIL,PIS,PIF, PME,PNR, PNX, PPI already update on raise_mmu_exception(),these are need't update.
Signed-off-by: Song Gao <[email protected]> --- target/loongarch/tcg/tcg_cpu.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 9d077c56d9..7f94c183c4 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -109,10 +109,22 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) } QEMU_FALLTHROUGH; case EXCCODE_PIF: - case EXCCODE_ADEF: cause = cs->exception_index; update_badinstr = 0; break; + case EXCCODE_ADEF: + update_badinstr = 0; + QEMU_FALLTHROUGH; + case EXCCODE_BCE: + case EXCCODE_ADEM: + env->CSR_BADV = env->pc; + QEMU_FALLTHROUGH; + case EXCCODE_PNR: + case EXCCODE_PNX: + case EXCCODE_PPI: + case EXCCODE_PIL: + case EXCCODE_PIS: + case EXCCODE_PME: case EXCCODE_SYS: case EXCCODE_BRK: case EXCCODE_INE: @@ -121,16 +133,6 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) case EXCCODE_FPE: case EXCCODE_SXD: case EXCCODE_ASXD: - env->CSR_BADV = env->pc; - QEMU_FALLTHROUGH; - case EXCCODE_BCE: - case EXCCODE_ADEM: - case EXCCODE_PIL: - case EXCCODE_PIS: - case EXCCODE_PME: - case EXCCODE_PNR: - case EXCCODE_PNX: - case EXCCODE_PPI: cause = cs->exception_index; break; default: -- 2.51.0
