From: "Xin Li (Intel)" <[email protected]> Both FRED and CET-SHSTK need MSR_IA32_PL0_SSP, so add the vmstate for this MSR.
When CET-SHSTK is not supported, MSR_IA32_PL0_SSP keeps accessible, but its value doesn't take effect. Therefore, treat this vmstate as a subsection rather than a fix for the previous FRED vmstate. Tested-by: Farrah Chen <[email protected]> Signed-off-by: Xin Li (Intel) <[email protected]> Co-developed-by: Zhao Liu <[email protected]> Signed-off-by: Zhao Liu <[email protected]> --- Changes Since v3: - New commit. --- target/i386/machine.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/i386/machine.c b/target/i386/machine.c index 45b7cea80aa7..0a756573b6cd 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1668,6 +1668,31 @@ static const VMStateDescription vmstate_triple_fault = { } }; +static bool pl0_ssp_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + +#ifdef TARGET_X86_64 + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { + return true; + } +#endif + + return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK); +} + +static const VMStateDescription vmstate_pl0_ssp = { + .name = "cpu/msr_pl0_ssp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pl0_ssp_needed, + .fields = (const VMStateField[]) { + VMSTATE_UINT64(env.pl0_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -1817,6 +1842,7 @@ const VMStateDescription vmstate_x86_cpu = { #endif &vmstate_arch_lbr, &vmstate_triple_fault, + &vmstate_pl0_ssp, NULL } }; -- 2.34.1
