On Tue, Nov 18, 2025 at 09:43:26AM +0100, Paolo Bonzini wrote: > Date: Tue, 18 Nov 2025 09:43:26 +0100 > From: Paolo Bonzini <[email protected]> > Subject: Re: [PATCH 2/5] i386/cpu: Cache EGPRs in CPUX86State > > On Tue, Nov 18, 2025 at 7:43 AM Zhao Liu <[email protected]> wrote: > > > > From: Zide Chen <[email protected]> > > > > Cache EGPR[16] in CPUX86State to store APX's EGPR value. > > Please change regs[] to have 32 elements instead; see the attached > patch for a minimal starting point. You can use VMSTATE_SUB_ARRAY to > split their migration data in two parts. You'll have to create a > VMSTATE_UINTTL_SUB_ARRAY similar to VMSTATE_UINT64_SUB_ARRAY.
Thanks! VMSTATE_UINTTL_SUB_ARRAY is for target_ulong. I'll move EGPRs to regs[]. > To support HMP you need to adjust target/i386/monitor.c and > target/i386/cpu-dump.c. Please make x86_cpu_dump_state print R16...R31 > only if APX is enabled in CPUID. > > Also, it would be best for the series to include gdb support. APX is > supported by gdb as a "coprocessor", the easiest way to do it is to > copy what riscv_cpu_register_gdb_regs_for_features() does for the FPU, > and copy > https://github.com/intel/gdb/blob/master/gdb/features/i386/64bit-apx.xml > into QEMU's gdb-xml/ directory. Good! Thank you for your guidance. I will add GDB support in next version. Regards, Zhao
