On 11/18/2025 1:54 PM, Sairaj Kodilkar wrote: > AMD IOMMU uses MMIO registers 0x170-0x180 to generate the interrupts when > guest > has enabled xt support through control register. The guest programs these > registers with appropriate vector and destination ID instead of writing to PCI > MSI capability. > > Until now enabling the xt support through command line "xtsup=on" provided > support for 128 bit IRTE. But it has few limitations: > > 1. It does not consider if guest has actually enabled xt support through MMIO > control register (0x18). This may cause problems for the guests which do > not enable this support. > 2. The vIOMMU is not capable of generating interrupts using vector and > destinatio ID in IOMMU x2APIC Control Registers (not supporting event log > interrupts). > > To overcome above limitations, this patch series introduces new internal flag > "intcapxten" which is set when guest writes "1" to MMIO control register > (0x18) > bit 51 (IntCapXTEn) and adds support to generate event log interrupt using > vector and 32 bit destination ID in XT MMIO register 0x170.
I have reviewed this series and it looks good. For entire series, Reviewed-by: Vasant Hegde <[email protected]> -Vasant
