On 11/19/25 8:27 AM, TravisYang wrote:
From: 杨智源 <[email protected]> Add a CPU entry for the RV64 THEAD C910 CPU which supports single-core and dual-core configurations.More details can be found at https://www.xrvm.cn/product/xuantie/C910?spm=a2d5.28054257.0.0.4a0f7a32qXoU1w Signed-off-by: TravisYang <[email protected]> ---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 47 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 75f4e43408..1fc8140190 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -56,6 +56,7 @@ #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu") +#define TYPE_RISCV_CPU_THEAD_C910 RISCV_CPU_TYPE_NAME("thead-c910") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ae8b721e55..f522bc856b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3281,6 +3281,53 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.max_satp_mode = VM_1_10_SV48, ),+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C910, TYPE_RISCV_VENDOR_CPU,+ .misa_mxl_max = MXL_RV64, + .misa_ext = RVG | RVC | RVS | RVU, + .priv_spec = PRIV_VERSION_1_12_0, + + .cfg.ext_zcf = true, + .cfg.ext_zcd = true, + .cfg.ext_zfa = true, + .cfg.ext_zfh = true, + .cfg.ext_zfhmin = true, + + .cfg.mmu = true, + .cfg.ext_xtheadba = true, + .cfg.ext_xtheadbb = true, + .cfg.ext_xtheadbs = true, + .cfg.ext_xtheadcmo = true, + .cfg.ext_xtheadcondmov = true, + .cfg.ext_xtheadfmemidx = true, + .cfg.ext_xtheadmac = true, + .cfg.ext_xtheadmemidx = true, + .cfg.ext_xtheadmempair = true, + .cfg.ext_xtheadsync = true, + .cfg.pmp = true, + + .cfg.ext_svinval = true, + .cfg.ext_svadu = true, + .cfg.ext_zicbom = true, + .cfg.ext_zicboz = true, + + .cfg.ext_zba = true, + .cfg.ext_zbb = true, + .cfg.ext_zbc = true, + .cfg.ext_zbs = true, + + .cfg.ext_zknd = true, + .cfg.ext_zkne = true, + .cfg.ext_zknh = true, + + .cfg.mvendorid = THEAD_VENDOR_ID, + + .cfg.max_satp_mode = VM_1_10_SV39, +#ifndef CONFIG_USER_ONLY + .custom_csrs = th_csr_list, +#endif + ), + + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV57,
