RISC-V instructions are always stored in little-endian order (see "Volume I: RISC-V Unprivileged ISA" document, chapter 'Instruction Encoding Spaces and Prefixes': "instruction fetch in RISC-V is little-endian").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/translate.c | 2 +- target/riscv/zce_helper.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e1f4dc5ffd0..847481a9b41 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1182,7 +1182,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) CPUState *cpu = ctx->cs; CPURISCVState *env = cpu_env(cpu); - return cpu_ldl_code(env, pc); + return cpu_ldl_le_code(env, pc); } #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE) diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c index 55221f5f375..992e2f964e0 100644 --- a/target/riscv/zce_helper.c +++ b/target/riscv/zce_helper.c @@ -44,10 +44,10 @@ target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) if (xlen == 32) { t0 = base + (index << 2); - target = cpu_ldl_code(env, t0); + target = cpu_ldl_le_code(env, t0); } else { t0 = base + (index << 3); - target = cpu_ldq_code(env, t0); + target = cpu_ldq_le_code(env, t0); } return target & ~0x1; -- 2.51.0
