From: Yannick Voßen <[email protected]> Registers are always 32 bit aligned. R_MAX is not the maximum register address, it is the maximum register number. The memory size can be determined by 4 * R_MAX.
Currently every register with an offset bigger than 0x40 will be ignored, because the memory size is set wrong. This effects the MCTRL register and makes it useless. This commit restores the correct behaviour. Cc: [email protected] Fixes: 034c2e69023 ("dma: Add Xilinx Zynq devcfg device model") Signed-off-by: YannickV <[email protected]> Reviewed-by: Edgar E. Iglesias <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> (cherry picked from commit a344e22917f48d8cd876d72057bcfb938beb0630) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 26845713ee..8141d46033 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -372,7 +372,7 @@ static void xlnx_zynq_devcfg_init(Object *obj) s->regs_info, s->regs, &xlnx_zynq_devcfg_reg_ops, XLNX_ZYNQ_DEVCFG_ERR_DEBUG, - XLNX_ZYNQ_DEVCFG_R_MAX); + XLNX_ZYNQ_DEVCFG_R_MAX * 4); memory_region_add_subregion(&s->iomem, A_CTRL, ®_array->mem); -- 2.47.3
