Currently RISC-V CPU has a property "debug" which is equivalent to old
debug specification v0.13 version. Now we have ratified debug
specification v1.0 version. To support both versions, we add "debug-1.0"
as one of RISC-V CPU property to let user specify that debug v0.13 or
debug v1.0 is enabled. When debug-1.0=false CPU fallbacks to default
v0.13 version.
Note that "debug-1.0" depends on "debug" property:
- debug=false,debug-1.0={true|false} --> debug is disabled
- debug=true,debug-1.0=false --> debug v0.13 is enabled
- debug=true,debug-1.0=true --> debug v1.0 is enabled
Signed-off-by: Alvin Chang <[email protected]>
Reviewed-by: Yu-Ming Chang <[email protected]>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg_fields.h.inc | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 73d4280..082035b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2637,6 +2637,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]
= {
static const Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+ DEFINE_PROP_BOOL("debug-1.0", RISCVCPU, cfg.debug_1_00, false),
{.name = "pmu-mask", .info = &prop_pmu_mask},
{.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */
diff --git a/target/riscv/cpu_cfg_fields.h.inc
b/target/riscv/cpu_cfg_fields.h.inc
index a154ecd..402b255 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -151,6 +151,7 @@ BOOL_FIELD(ext_XVentanaCondOps)
BOOL_FIELD(mmu)
BOOL_FIELD(pmp)
BOOL_FIELD(debug)
+BOOL_FIELD(debug_1_00)
BOOL_FIELD(misa_w)
BOOL_FIELD(short_isa_string)
--
2.43.0
