On Tue, 2 Dec 2025 at 14:29, Gustavo Romero <[email protected]> wrote: > Afaics, we are not flushing the TLB here like we do for TCR_ELx (in > vmsa_tcr_el12_write) before > we call raw_write(). Since here we could be changing the A2 & friends bits, > which can change > the value of the ASID being using (like the TCR_ELx.A1 bit), I believe we > should flush the TLB > explicitly here like we do in vmsa_tcr_el12_write(). > > @rth wdyt?
I agree; the guest could reasonably expect TLB entries previously in use to stop being matched. In any case, I don't imagine flushing the TLB here will be a significant performance problem. Good spot! Jim
