From: Frank Chang <[email protected]>
This patch series fixes the spurious IRQ issue in the SiFive UART on Linux
introduced after commit [1], which changed character transmission from
synchronous to asynchronous.
Currently, the txwm interrupt pending status is only updated when the
asynchronous transmit handler runs. This can cause the txwm interrupt
state to become unsynchronized between the SiFive UART and the interrupt
controller.
This issue has been observed on resource-constrained systems, where
Linux reports spurious IRQ errors. In these cases, the asynchronous
transmit handler is unable to drain the TX FIFO quickly enough to update
the txwm pending status before software reads the IP register, which
derives the txwm pending state directly from the actual number of
characters in the TX FIFO.
The remaining patches contain miscellaneous updates, including
implementing txctrl.txen and rxctrl.rxen, update IRQ when rxctrl is
written and remove the unused ip variable.
[1] 53c1557b230986ab6320a58e1b2c26216ecd86d5
Frank Chang (4):
hw/char: sifive_uart: Implement txctrl.txen and rxctrl.rxen
hw/char: sifive_uart: Sync txwm interrupt pending status after TX FIFO
enqueue
hw/char: sifive_uart: Update IRQ when rxctrl is written
hw/char: sifive_uart: Remove ip variable
hw/char/sifive_uart.c | 46 ++++++++++++++++++++++++++++-------
include/hw/char/sifive_uart.h | 3 ++-
2 files changed, 39 insertions(+), 10 deletions(-)
--
2.43.0
