On Mon, Dec 08 2025, Eric Auger <[email protected]> wrote: > Generated definitions with scripts/update-aarch64-sysreg-code.py > based on "AARCHMRS containing the JSON files for Arm A-profile > architecture (2025-09)" Registers.json file. > > Signed-off-by: Eric Auger <[email protected]> > --- > target/arm/cpu-sysregs.h.inc | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc > index 3c892c4f30..9bb27297b5 100644 > --- a/target/arm/cpu-sysregs.h.inc > +++ b/target/arm/cpu-sysregs.h.inc > @@ -1,17 +1,27 @@ > -/* SPDX-License-Identifier: GPL-2.0-or-later */ > +/* SPDX-License-Identifier: BSD-3-Clause */ > + > +/* This file is autogenerated by scripts/update-aarch64-sysreg-code.py */ > + > +DEF(AIDR_EL1, 3, 1, 0, 0, 7)
AIDR_EL1 (and MIDR_EL1/REVIDR_EL1) are used by the (hopefully-soon-respun) writable id register series, so it's good that they do not need to be added by hand anymore :) > DEF(CLIDR_EL1, 3, 1, 0, 0, 1) > DEF(CTR_EL0, 3, 3, 0, 0, 1) > +DEF(DCZID_EL0, 3, 3, 0, 0, 7) Also see https://lore.kernel.org/qemu-devel/[email protected]/T/#u > +DEF(GMID_EL1, 3, 1, 0, 0, 4) > DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) > DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) > DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) > DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) > +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) > +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) > DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) > DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) > DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) > +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3) > DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) > DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) > DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) > DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) > +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) > DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) > DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) > DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) > @@ -36,6 +46,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) > DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) > DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) > DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) > +DEF(MIDR_EL1, 3, 0, 0, 0, 0) > +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) I'm wondering if we need to add some handling for MPIDR_EL1. > DEF(MVFR0_EL1, 3, 0, 0, 3, 0) > DEF(MVFR1_EL1, 3, 0, 0, 3, 1) > DEF(MVFR2_EL1, 3, 0, 0, 3, 2) > +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) > +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) SMIDR_EL1 is const 0 in tcg, and KVM currently does not support SME. So I guess we should init the idreg to 0 for now?
