Hi Yubin, In my local testing, your code changes work well. Please also review my comments in the other emails.
Thank you for your help in adding the SGPIO module. Best Regards, Kane > -----Original Message----- > From: Yubin Zou <[email protected]> > Sent: Thursday, December 11, 2025 7:29 AM > To: [email protected] > Cc: Cédric Le Goater <[email protected]>; Peter Maydell > <[email protected]>; Steven Lee <[email protected]>; Troy > Lee <[email protected]>; Jamin Lin <[email protected]>; Andrew > Jeffery <[email protected]>; Joel Stanley <[email protected]>; > Fabiano Rosas <[email protected]>; Laurent Vivier <[email protected]>; > Paolo Bonzini <[email protected]>; Kane Chen > <[email protected]>; Nabih Estefan <[email protected]>; > [email protected]; Yubin Zou <[email protected]> > Subject: [PATCH v3 0/6] hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO > (SGPIO) controller model > > This series introduces a model for the Aspeed Serial GPIO (SGPIO) controller, > commonly found on Aspeed SoCs such as the AST2700. The SGPIO peripheral > provides a large number of GPIO pins that can be controlled and monitored > serially. > > Improvement to QEMU: > These patches enhance QEMU's hardware emulation capabilities for platforms > using Aspeed SoCs, particularly for BMC simulations. By modeling the SGPIO > controller, QEMU can more accurately represent the hardware, allowing for > better development and testing of firmware and software that relies on these > GPIOs for various functions like sensor monitoring, presence detect, and > system control signals. > > Impact (Before/After): > > Before: > QEMU lacked a model for the Aspeed SGPIO controller. Any guest software > attempting to interact with the SGPIO register space would find no device. > Firmware features depending on SGPIO pin states or interrupts could not be > tested in QEMU. > > After: > QEMU emulates the Aspeed SGPIO controller on supported machines (e.g., > ast2700-evb). > - Guest firmware can configure SGPIO pins, set output values, and read input > values through the memory-mapped registers. > - External entities (like test scripts or other QEMU components) can interact > with the pins via QOM properties (e.g., to simulate external signal > changes). > Path example: /machine/soc/sgpio[0]/sgpio0 > - The model generates interrupts based on input pin transitions, according to > the configured mode (level/edge), enabling testing of interrupt handlers. > > Signed-off-by: Yubin Zou <[email protected]> > --- > Changes in v3: > - Fix commit message typo and address several review feedback in > commit 2/6. > - Switch to use g_autofree and drop g_free. > - Use "%03d" instead of "%d". > - Link to v2: > https://lore.kernel.org/qemu-devel/20251209-aspeed-sgpio-v2-0-976e5f5790 > [email protected] > > Changes in v2: > Split the v1 into smaller commits and reorder it for better review: > - Link to v1: > https://lore.kernel.org/qemu-devel/20251106-aspeed-sgpio-v1-0-b02609371 > [email protected] > > --- > Yubin Zou (6): > hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO > hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins > hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling > hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO > controllers > hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC > test/qtest: Add Unit test for Aspeed SGPIO > > include/hw/arm/aspeed_soc.h | 8 +- > include/hw/gpio/aspeed_sgpio.h | 68 ++++++++ > hw/arm/aspeed_ast10x0.c | 6 +- > hw/arm/aspeed_ast27x0.c | 26 +++ > hw/gpio/aspeed_sgpio.c | 348 > +++++++++++++++++++++++++++++++++++++++ > tests/qtest/ast2700-sgpio-test.c | 152 +++++++++++++++++ > hw/gpio/meson.build | 1 + > tests/qtest/meson.build | 1 + > 8 files changed, 605 insertions(+), 5 deletions(-) > --- > base-commit: 917ac07f9aef579b9538a81d45f45850aba42906 > change-id: 20251105-aspeed-sgpio-1d49de6cea66 > > Best regards, > -- > Yubin Zou <[email protected]>
