Hi Fabiano,
On 2025/12/12 23:31, Fabiano Rosas wrote:
Tao Tang <[email protected]> writes:
Add a minimal PCI test device designed to exercise IOMMU translation
(such as ARM SMMUv3) without requiring guest firmware or OS. The device
provides MMIO registers to configure and trigger DMA operations with
controllable attributes (security state, address space), enabling
deterministic IOMMU testing.
Key features:
- Bare-metal IOMMU testing via simple MMIO interface
- Configurable DMA attributes for security states and address spaces
- Write-then-read verification pattern with automatic result checking
The device performs a deterministic DMA test pattern: write a known
value (0x88888888) to a configured IOVA, read it back, and verify data
integrity. Results are reported through a dedicated result register,
eliminating the need for complex interrupt handling or driver
infrastructure in tests.
This is purely a test device and not intended for production use or
machine realism. It complements existing test infrastructure like
pci-testdev but focuses specifically on IOMMU translation path
validation.
Signed-off-by: Tao Tang <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
---
docs/specs/index.rst | 1 +
docs/specs/iommu-testdev.rst | 109 +++++++++++++
hw/misc/Kconfig | 5 +
hw/misc/iommu-testdev.c | 278 ++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 10 ++
include/hw/misc/iommu-testdev.h | 70 ++++++++
7 files changed, 474 insertions(+)
create mode 100644 docs/specs/iommu-testdev.rst
create mode 100644 hw/misc/iommu-testdev.c
create mode 100644 include/hw/misc/iommu-testdev.h
------------------------------<snip>------------------------------
------------------------------<snip>------------------------------
+
+/* DMA result/status values shared with tests */
+#define ITD_DMA_RESULT_IDLE 0xffffffffu
+#define ITD_DMA_RESULT_BUSY 0xfffffffeu
+#define ITD_DMA_ERR_BAD_LEN 0xdead0001u
+#define ITD_DMA_ERR_TX_FAIL 0xdead0002u
+#define ITD_DMA_ERR_RD_FAIL 0xdead0003u
+#define ITD_DMA_ERR_MISMATCH 0xdead0004u
+#define ITD_DMA_ERR_NOT_ARMED 0xdead0005u
+
+#define ITD_DMA_WRITE_VAL 0x88888888u
Is this intended to read the same regardless of endianness? It would
mask possible endianness bugs.
Thanks for catching this.
It was something I typed quickly, and I did overlook endianness at the
time. I’ll change it to 0x12345678 in the next revision.
Best regard,
Tao
For the rest of the patch:
Reviewed-by: Fabiano Rosas <[email protected]>
