Adds macros and global interfaces for defining machines available only
in qemu-system-riscv32, qemu-system-riscv64, or both.

Signed-off-by: Anton Johansson <[email protected]>
---
 include/hw/riscv/machines-qom.h | 26 ++++++++++++++++++++++++++
 target/riscv/machine.c          | 17 +++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 6e2c542c87..2254b2dbcc 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -17,4 +17,30 @@
 #define TYPE_TARGET_RISCV64_MACHINE \
         "target-info-riscv64-machine"
 
+/*
+ * Interfaces specifiying wether a given QOM object is available in
+ * qemu-system-riscv32, qemu-riscv-riscv64, or both.
+ */
+
+extern InterfaceInfo riscv32_machine_interfaces[];
+extern InterfaceInfo riscv64_machine_interfaces[];
+extern InterfaceInfo riscv32_64_machine_interfaces[];
+
+/*
+ * Helper macros for defining machines available in qemu-system-riscv32,
+ * qemu-system-riscv64, or both.
+ */
+
+#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
+        DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+                                            riscv32_machine_interfaces)
+
+#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
+        DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+                                            riscv64_machine_interfaces)
+
+#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
+        DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+                                            riscv32_64_machine_interfaces)
+
 #endif
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 13eb292c4a..3d2e3968fd 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -23,6 +23,7 @@
 #include "migration/cpu.h"
 #include "exec/icount.h"
 #include "target/riscv/debug.h"
+#include "hw/riscv/machines-qom.h"
 
 static bool pmp_needed(void *opaque)
 {
@@ -503,3 +504,19 @@ const VMStateDescription vmstate_riscv_cpu = {
         NULL
     }
 };
+
+InterfaceInfo riscv32_machine_interfaces[] = {
+    { TYPE_TARGET_RISCV32_MACHINE },
+    { }
+};
+
+InterfaceInfo riscv64_machine_interfaces[] = {
+    { TYPE_TARGET_RISCV64_MACHINE },
+    { }
+};
+
+InterfaceInfo riscv32_64_machine_interfaces[] = {
+    { TYPE_TARGET_RISCV32_MACHINE },
+    { TYPE_TARGET_RISCV64_MACHINE },
+    { }
+};

-- 
2.51.0


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