On Mon, 3 Nov 2025 11:52:05 -0800 Davidlohr Bueso <[email protected]> wrote:
> PCIe Flit Mode, introduced with the PCIe 6.0 specification, is a > fundamental change in how data is transmitted over the bus to > improve transfer rates. It shifts from variable-sized Transaction > Layer Packets (TLPs) to fixed 256-byte Flow Control Units (FLITs). > > As with the link speed and width training, have ad-hoc property for > setting the flit mode and allow CXL components to make use of it. > > For the CXL root port and dsp cases, always report flit mode but > the actual value after 'training' will depend on the downstream > device configuration. > > Suggested-by: Jonathan Cameron <[email protected]> > Tested-by: Dongjoo Seo <[email protected]> > Signed-off-by: Davidlohr Bueso <[email protected]> One small question inline. > diff --git a/hw/pci-bridge/gen_pcie_root_port.c > b/hw/pci-bridge/gen_pcie_root_port.c > index d9078e783bf0..6b97da0b4cbb 100644 > --- a/hw/pci-bridge/gen_pcie_root_port.c > +++ b/hw/pci-bridge/gen_pcie_root_port.c > @@ -145,6 +145,7 @@ static const Property gen_rp_props[] = { > speed, PCIE_LINK_SPEED_16), > DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, > width, PCIE_LINK_WIDTH_32), > + DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, false), Do we need this given we only care about this mode for CXL devices? Will default to false anyway and seems unwise to add infrastructure when nothing that can be connected below this uses it yet. > }; > > static void gen_rp_dev_class_init(ObjectClass *klass, const void *data)
