Ordering rule 3 preceding the isa_edata_arr[] array requires alphabetical
ordering of standard supervisor-level extensions.
The sha extension needs to be placed before shcounterenw. This change also
corrects the riscv,isa string generated for cpus which includes them,
such as rva23s64.
Verified by
qemu-system-riscv64 \
-machine virt,acpi=off \
-cpu rva23s64 \
...
/proc/device-tree/cpus/cpu@0 # cat riscv,isa
Signed-off-by: Guodong Xu <[email protected]>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
73d4280d7c84a9d4c7cecd3e067d312adc13b035..e24f32978f645d71d149e0f06c31ce848876f636
100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -190,8 +190,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
- ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
+ ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
---
base-commit: bb7fc1543fa45bebe7eded8115f25441a9fee76e
change-id: 20251220-sha-96f1ce1f3337
Best regards,
--
Guodong Xu <[email protected]>
