Compiles hw/riscv a single time for both qemu-system-riscv32 and
qemu-system-riscv64 by adopting the TargetInfo API and by moving
machine definitions to generic QOM interfaces. This is the same approach
as taken by Philippe in
"single-binary: Make hw/arm/ common"
([email protected]).
All in all, the number of compilation when building both
riscv[32|64]-softmmu is reduced by 11, and the binary size of
qemu-system-riscv[32|64] is increased by 0.14% and 0.11% respectively
(corresponding to 73k and 57k bytes).
This patches is based on the following patchsets, applied in descending
order:
- "single-binary: Make riscv cpu.h target partially independent"
([email protected]);
- "single-binary: Make riscv cpu.h target independent"
([email protected]);
- "hw/riscv: Treat kernel_start_addr as vaddr"
([email protected]);
- "single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS"
([email protected]).
Branch passing CI can be found here:
https://gitlab.com/AntonJohansson/qemu/-/pipelines/2215536778
Signed-off-by: Anton Johansson <[email protected]>
---
Changes in v2:
- Inlined sifive_cpu.h runtime functions and removed header (Philippe);
- Moved IRQ_LOCAL_GUEST_MAX macro to field in RISCVCPUDef (Philippe);
- Added reviewed-bys;
- Link to v1:
https://lore.kernel.org/qemu-devel/[email protected].
---
Anton Johansson (14):
hw/riscv: Register generic riscv[32|64] QOM interfaces
hw/riscv: Add macros and globals for simplifying machine definitions
hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries
hw/core: Add riscv[32|64] to "none" machine
configs/target: Implement per-binary TargetInfo structure for riscv
target-info: Add target_riscv64()
target/riscv: Replace TYPE_RISCV_CPU_BASE
target/riscv: Remove ifdefs in cpu.h
target/riscv: Replace TARGET_LONG_BITS in header exposed to common code
target/riscv: Move riscv_pmu_read_ctr() to internal csr.h header
target/riscv: Make pmu.h target-agnostic
target/riscv: Stub out kvm functions
hw/riscv: Define SiFive E/U CPUs using runtime conditions
hw/riscv: Compile once
include/hw/riscv/machines-qom.h | 46 +++++++++++++++++++++++++++++++++++++++
include/hw/riscv/sifive_cpu.h | 31 --------------------------
include/hw/riscv/sifive_e.h | 1 -
include/hw/riscv/sifive_u.h | 1 -
include/hw/riscv/virt.h | 11 ++++++++++
include/qemu/target-info.h | 7 ++++++
target/riscv/cpu.h | 43 ++++++++----------------------------
target/riscv/cpu_bits.h | 2 --
target/riscv/csr.h | 3 +++
target/riscv/pmu.h | 4 +---
configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++
configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++
hw/core/null-machine.c | 3 +++
hw/intc/riscv_imsic.c | 4 +++-
hw/riscv/microblaze-v-generic.c | 6 +++--
hw/riscv/microchip_pfsoc.c | 2 ++
hw/riscv/opentitan.c | 2 ++
hw/riscv/shakti_c.c | 2 ++
hw/riscv/sifive_e.c | 5 ++++-
hw/riscv/sifive_u.c | 9 ++++++--
hw/riscv/spike.c | 5 ++++-
hw/riscv/virt.c | 5 ++++-
hw/riscv/xiangshan_kmh.c | 2 ++
target-info-qom.c | 9 ++++++++
target-info.c | 5 +++++
target/riscv/cpu.c | 14 ++++++++++--
target/riscv/kvm/kvm-stub.c | 23 ++++++++++++++++++++
target/riscv/machine.c | 17 +++++++++++++++
target/riscv/pmu.c | 9 +++++---
configs/targets/meson.build | 1 +
hw/riscv/meson.build | 32 +++++++++++++--------------
target/riscv/kvm/meson.build | 1 +
32 files changed, 256 insertions(+), 101 deletions(-)
