On Mon, Jun 11, 2012 at 10:03:56AM -0500, Anthony Liguori wrote: > On 06/11/2012 09:53 AM, Peter Maydell wrote: > >On 11 June 2012 15:38, Edgar E. Iglesias<edgar.igles...@gmail.com> wrote: > >>On Mon, Jun 11, 2012 at 02:39:56PM +0100, Peter Maydell wrote: > >>>Ideally the interface used by DMA controllers should be identical to > >>>the interface used by CPUs to talk to the rest of the system: it's > >>>exactly the same bus interface in hardware, after all. > >> > >>I thought we were talking about the interface between the DMA ctrl > >>and the I/O (devices). Not between the DMA and the "memory" bus system. > > > >In hardware (at least for AXI) they're the same thing. A DMA > >controller is a bus master, just like a CPU. They don't care > >whether the slave is RAM or a device, they're just issuing > >memory transactions to addresses. > > It looks like the AXI stream interface also includes a word array. > I can't tell though whether this is just a decomposed scatter/gather > list though.
Hi, IIRC the word array thing is device specific, not really AXI stream. I think the whole connection to AXI is a bit unfortunate, these devices are pretty much the same devices that in other contexts where connected to other bus standards. Xilinx choose to name them AXI-xxx and I used the name in our models but I didn't really model anything that is AXI stream specific.. > There doesn't appear to be a notion of an address though. You could > make all operations go to address 0 though but it makes me wonder if > that's stretching the concept of DMA a bit too much. Yes, IMO we need a different abstraction.. Cheers
