On Fri, Mar 6, 2026 at 5:13 PM Max Chou <[email protected]> wrote: > > This patch series adds support for the RISC-V Zvfbfa extension, which > provides additional BF16 vector compute support. > > The isa spec of Zvfbfa extension is not ratified yet, so this patch > series is based on the latest draft of the spec (v0.1) and make the > Zvfbfa extension as an experimental extension.
It's not only not ratified, there isn't even a draft spec. A personal GitHub repo without any tags or releases is not enough for us to take this unfortunately. > > The Zvfbfa extension adds a 1-bit field, altfmt, to the vtype CSR in > bit position 8. > The Zvfbfa extension requires the Zve32f and Zfbfmin extensions. > > Specification: > https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc Overall this looks ok. Once a draft spec is released we can apply it Alistair > > Changes in v5: > - Fix typo in patch 1/5/8 > - Remove unnecessary do_bf16_nanbox > > Changes in v4: > - Rebase on riscv-to-apply.next (commit 21101a7) > - Update commit message of patch 2 (target/riscv: Add the Zvfbfa > extension implied rule) > - Update checking flow of illegal ALTFMT SEW patterns at patch 3 > (target/riscv: rvv: Add new VTYPE CSR field - altfmt) > > Changes in v3: > - Rebased on riscv-to-apply.next (commit f66f234) > - Fix typo in v2 patch 5 commit message > > Changes from v2: > - Removed RFC designation from the series > - Updated commit message for patch 3 (VTYPE CSR field - > altfmt) to clearly explain: > * VEDIV field removal (bits 8-9) since EDIV extension is not > planned to be part of the base V extension > * ALTFMT field addition at bit 8 > * RESERVED field change from bit 10 to bit 9 > - Added new patch 4: Introduce reset_ill_vtype helper function to > consolidate illegal vtype CSR reset logic > > v4: <[email protected]> > v3: <[email protected]> > v2: <[email protected]> > v1: <[email protected]> > > rnax > > > Max Chou (9): > target/riscv: Add cfg properties for Zvfbfa extensions > target/riscv: Add the Zvfbfa extension implied rule > target/riscv: rvv: Add new VTYPE CSR field - altfmt > target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype > CSR > target/riscv: Use the tb->cs_base as the extend tb flags > target/riscv: Introduce altfmt into DisasContext > target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension > target/riscv: rvv: Support Zvfbfa vector bf16 operations > target/riscv: Expose Zvfbfa extension as an experimental cpu property > > include/exec/translation-block.h | 1 + > target/riscv/cpu.c | 15 +- > target/riscv/cpu.h | 7 +- > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/helper.h | 60 ++ > target/riscv/insn_trans/trans_rvv.c.inc | 988 +++++++++++++++--------- > target/riscv/internals.h | 1 + > target/riscv/tcg/tcg-cpu.c | 15 +- > target/riscv/translate.c | 11 + > target/riscv/vector_helper.c | 389 +++++++++- > 10 files changed, 1088 insertions(+), 400 deletions(-) > > -- > 2.52.0 > >
