Reorganised as a vendor extension for Ibex and renamed to xbr0p93. James Wainwright (3): util: export CRC32[C] lookup tables target/riscv: add draft RISC-V Zbr ext as xbr0p93 disas: diassemble RISC-V Zbr0p93 instructions
MAINTAINERS | 2 +- disas/meson.build | 3 +- disas/riscv-xbr0p93.c | 79 +++++++++++++++++++ disas/riscv-xbr0p93.h | 19 +++++ disas/riscv.c | 4 + include/qemu/crc32.h | 18 +++++ include/qemu/crc32c.h | 1 + target/riscv/bitmanip_helper.c | 20 +++++ target/riscv/cpu.c | 4 +- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/helper.h | 2 + target/riscv/insn_trans/trans_xbr0p93.c.inc | 55 +++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 + target/riscv/xbr0p93.decode | 42 ++++++++++ tests/tcg/riscv64/Makefile.softmmu-target | 5 ++ tests/tcg/riscv64/test-crc32.S | 64 ++++++++++++++++ util/crc32.c | 85 +++++++++++++++++++++ util/crc32c.c | 4 +- util/meson.build | 1 + 21 files changed, 409 insertions(+), 5 deletions(-) create mode 100644 disas/riscv-xbr0p93.c create mode 100644 disas/riscv-xbr0p93.h create mode 100644 include/qemu/crc32.h create mode 100644 target/riscv/insn_trans/trans_xbr0p93.c.inc create mode 100644 target/riscv/xbr0p93.decode create mode 100644 tests/tcg/riscv64/test-crc32.S create mode 100644 util/crc32.c -- 2.48.1
