This patch series adds support for the ARM Large Physical Address Extensions, which allow 40 bit physical addressing by means of a new translation table format.
Patches 1-3 are all dependencies which have been posted to the list separately already. Patch 4 makes target_phys_addr_t 64 bits for ARM. Patch 5 adds privileged-execute-never to the existing short descriptor translation table code; this is a potentially independent feature which is required by LPAE. Patch 6 extends the ARMCPUState feature flag bitfield to 64 bits, since patch 5 just used up the last bit in the 32 bit word. Patches 7-13 actually implement LPAE. I believe this to be a complete implementation of LPAE, with the caveat that we don't actually do anything with memory attributes or cacheability attributes and we don't enforce memory access alignment restrictions. These are all things QEMU doesn't do in the non-LPAE case either (and which it seems unlikely that we'll support any time soon). It's possible that making target_phys_addr_t 64 bits for all ARM cores might be a slight slowdown (though only in system mode, and not in the fast path of a TLB hit for a RAM access). Benchmarking this is on my todo list, but I wanted to put the patchset out for review to start with. (The only alternative I can think of to widening target_phys_addr_t would be putting A15 in a separate qemu-system-* binary, which seems like a pretty awful idea.) Peter Maydell (13): hw/cadence_gem: Make rx_desc_addr and tx_desc_addr uint32_t target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 bitops.h: Add functions to extract and deposit bitfields ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits target-arm: Implement privileged-execute-never (PXN) target-arm: Extend feature flags to 64 bits target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE target-arm: Use target_phys_addr_t in get_phys_addr() target-arm: Implement long-descriptor PAR format target-arm: Implement TTBCR changes for LPAE target-arm: Add support for long format translation table walks bitops.h | 66 ++++++++ configure | 2 +- hw/cadence_gem.c | 4 +- target-arm/cpu.c | 6 +- target-arm/cpu.h | 15 ++- target-arm/helper.c | 435 +++++++++++++++++++++++++++++++++++++++++++++----- target-arm/machine.c | 10 +- 7 files changed, 489 insertions(+), 49 deletions(-)
