The actual implementation supports the additional trapping registers of HCR_TTLBIS | HCR_TTLBOS. We already set the value to 2 for -cpu max and don't currently model any CPUs that only have FEAT_EVT.
Signed-off-by: Alex Bennée <[email protected]> --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-max.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 4f413d69efc..fb8d263db49 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -68,6 +68,7 @@ the following architecture extensions: - FEAT_EPAC (Enhanced pointer authentication) - FEAT_ETS2 (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) +- FEAT_EVT2 (Enhanced Virtualization Traps 2) - FEAT_F8F16MM (8-bit floating-point matrix multiply-accumulate to half-precision) - FEAT_F8F32MM (8-bit floating-point matrix multiply-accumulate to single-precision) - FEAT_F32MM (Single-precision Matrix Multiplication) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index d38bdfcf811..88b7c046333 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -130,7 +130,7 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ - t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ + t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ SET_IDREG(isar, ID_MMFR4, t); FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ -- 2.47.3
