From: Jagan <402ja...@gmail.com>
This patch adds support for NOR0 flash (Bank #1) on
vexpress-a9 platform. It is 64MB CFI01 compliant flash.
Tested on stable u-boot version through Linux.
Signed-off-by: Jagan <402ja...@gmail.com>
---
hw/vexpress.c | 17 ++++++++++++++++-
1 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 8072c5a..2e889a8 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -29,6 +29,11 @@
#include "sysemu.h"
#include "boards.h"
#include "exec-memory.h"
+#include "blockdev.h"
+#include "flash.h"
+
+#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
+#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
#define VEXPRESS_BOARD_ID 0x8e0
@@ -355,6 +360,7 @@ static void vexpress_common_init(const VEDBoardInfo
*daughterboard,
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
const target_phys_addr_t *map = daughterboard->motherboard_map;
+ DriveInfo *dinfo;
daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id);
@@ -405,7 +411,16 @@ static void vexpress_common_init(const VEDBoardInfo
*daughterboard,
sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
- /* VE_NORFLASH0: not modelled */
+ /* VE_NORFLASH0: */
+ dinfo = drive_get(IF_PFLASH, 0, 0);
+ if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
+ VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
+ VEXPRESS_FLASH_SECT_SIZE,
+ VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE,
+ 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
+ fprintf(stderr, "qemu: Error registering flash0 memory.\n");
+ }
+
/* VE_NORFLASH0ALIAS: not modelled */
/* VE_NORFLASH1: not modelled */
--
1.7.0.4
