I wanted to add some new insns, so that I could start testing gcc changes for z10+, but found the more or less ad-hoc disassembly routines difficult and error prone.
I've begun rewriting the translator into a more table-driven approach, which I have so far found much easier to manage. I'd hoped to get all of the insns converted before the weekend, but there's 14 control insns left and I've run out of time. The approach assumes we don't care about performance on a 32-bit host. In practice we can't run anything on such a one anyway. Therefore we handle everything as a TCGv_i64 and be done with it. This greatly simplifies things. Translation proceeds by calling a sequence of small functions to load up the arguments as directed by the insn and the format, perform the operation, and setup the condition codes. All of the hooks are optional, and in extremis the operation can handle all of its arguments itself. This is not uncommon in some of the string functions where we simply load up register numbers and pass those down to a helper func. The current branch consists of 102 patches, most of which convert one or two instruction (groups) at a time. The format of the table went through at least 4 revisions, all but the last of which have been compressed together. Thus ignore the form of the table before patch 15: "Reboot^2 reorg". And because of that I'll not bother posting patches here yet, and simply direct those interested to git://repo.or.cz/qemu/rth.git rth/s390-reorg While I'll probably keep working on this for myself in either case, I'm wondering about commitment to reviewing this monster. I'm also of course interested in obvious errors and the like as well. r~
