On Mon, Sep 10, 2012 at 04:58:39PM +0200, Andreas Färber wrote: > Am 10.09.2012 16:50, schrieb Don Slutz: > > On 09/10/12 09:04, Igor Mammedov wrote: > >> But question unrelated to this patch is still stand if ia64 is valid > >> bit for > >> 01.EDX[30]? > >> > >> > > Intel® Processor Identification > > and the CPUID Instruction > > Application Note 485 > > January 2006 > > > > Order Number: 241618-030 > > > > ... > > > > Updated Table 3-5 to include the feature flag definition (EDX[30]) for > > IA64 capabilities. > > ... > > 30 IA64 IA64 Capabilities The processor is a member of the Intel® > > Itanium® processor family > > and currently operating in IA32 emulation mode. > > > > --------------- > > > > Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and > > http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) > > Don't those semantics contradict the use in qemu-system-x86_64 or > qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia64 > CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag could > never become 1 IIUC.
Correct, and the bit is always filtered out on both TCG and KVM modes. The name is in the table because we know the name/meaning of that feature bit, but it's impossible to enable it. That said, I don't mind removing it from the table just to avoid confusion, but I also wouldn't mind keeping it (as it's harmless). -- Eduardo
