Ping! Should this go via arm-devs or create a zynq-specific queue?
Regards, Peter On Thu, Sep 27, 2012 at 11:18 AM, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote: > From: Soren Brinkmann <soren.brinkm...@xilinx.com> > > A missing call to qemu_set_irq() when reading the IRQ register > required SW to write to the IRQ register to acknowledge an > interrupt. With this patch the behavior is fixed: > - Reading the interrupt register clears it and updates the timers > interrupt status > - Writes to the interrupt register are ignored > > Signed-off-by: Soren Brinkmann <soren.brinkm...@xilinx.com> > Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com> > --- > hw/cadence_ttc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c > index dd02f86..77b6976 100644 > --- a/hw/cadence_ttc.c > +++ b/hw/cadence_ttc.c > @@ -274,6 +274,7 @@ static uint32_t cadence_ttc_read_imp(void *opaque, > target_phys_addr_t offset) > /* cleared after read */ > value = s->reg_intr; > s->reg_intr = 0; > + cadence_timer_update(s); > return value; > > case 0x60: /* interrupt enable */ > @@ -355,7 +356,6 @@ static void cadence_ttc_write(void *opaque, > target_phys_addr_t offset, > case 0x54: /* interrupt register */ > case 0x58: > case 0x5c: > - s->reg_intr &= (~value & 0xfff); > break; > > case 0x60: /* interrupt enable */ > -- > 1.7.12.1.396.g16eed7c > >
