From: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
This doesn't happen in the real hardware. The Zynq TRM explicitly states that
this bit has no effect on the rx descriptor pointer ("The receive queue
pointer register is unaffected").
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Message-id:
06fdf92b78ee62d8965779bafd29c8df1a5d2718.1360901435.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
hw/cadence_gem.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
index a1ac069..61f1801 100644
--- a/hw/cadence_gem.c
+++ b/hw/cadence_gem.c
@@ -1083,10 +1083,6 @@ static void gem_write(void *opaque, hwaddr offset,
uint64_t val,
/* Reset to start of Q when transmit disabled. */
s->tx_desc_addr = s->regs[GEM_TXQBASE];
}
- if (!(val & GEM_NWCTRL_RXENA)) {
- /* Reset to start of Q when receive disabled. */
- s->rx_desc_addr = s->regs[GEM_RXQBASE];
- }
if (val & GEM_NWCTRL_RXENA) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
--
1.7.9.5
