On Sun, Feb 10, 2013 at 10:30:48AM -0800, Richard Henderson wrote:
> COP1X refers to the availability of indexed memory operations,
> not whether the FPU has 64-bit registers.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target-mips/translate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index b3b8dc6..a39e118 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1366,8 +1366,9 @@ static inline void check_cop1x(DisasContext *ctx)
>
> static inline void check_cp1_64bitmode(DisasContext *ctx)
> {
> - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
> + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64))) {
> generate_exception(ctx, EXCP_RI);
> + }
> }
>
I think this is wrong. This check comes from the following patch:
http://lists.gnu.org/archive/html/qemu-devel/2007-12/msg00581.html
In short check_cp1_64bitmode() is called for COP1X instructions (nabla
ones) which need the FPU in 64-bit mode. COP1X instructions might not
always been able and might have to be activated (CU3 on MIPS IV, 64-bit
operations enabled on MIPS64R1), so checking the ISA is not enough.
Maybe the name is misleading, but IMHO the behavior is correct.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net
