Signed-off-by: Laszlo Ersek <ler...@redhat.com>
---
hw/pc.h | 3 +
hw/acpi.c | 7 +--
hw/i386/pc.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 134 insertions(+), 4 deletions(-)
diff --git a/hw/pc.h b/hw/pc.h
index b8574a2..2a4358f 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -113,6 +113,9 @@ extern char unsigned *acpi_tables;
extern size_t acpi_tables_len;
void acpi_bios_init(void);
+void acpi_table_install(const char unsigned *blob, size_t bloblen,
+ bool has_header, const struct AcpiTableOptions *hdrs,
+ Error **errp);
void acpi_table_add(const QemuOpts *opts, Error **errp);
/* acpi_piix.c */
diff --git a/hw/acpi.c b/hw/acpi.c
index e7a213c..58b5afd 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -95,10 +95,9 @@ static int acpi_checksum(const uint8_t *data, int len)
* The number of tables that can be installed is not limited, but the 16-bit
* counter at the beginning of "acpi_tables" wraps around after UINT16_MAX.
*/
-static void acpi_table_install(const char unsigned *blob, size_t bloblen,
- bool has_header,
- const struct AcpiTableOptions *hdrs,
- Error **errp)
+void acpi_table_install(const char unsigned *blob, size_t bloblen,
+ bool has_header, const struct AcpiTableOptions *hdrs,
+ Error **errp)
{
size_t body_start;
const char unsigned *hdr_src;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0a5d4d4..331eb60 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -886,6 +886,132 @@ void pc_cpus_init(const char *cpu_model)
}
}
+static void pc_acpi_madt(void)
+{
+ typedef struct {
+ uint8_t type;
+ uint8_t length;
+ } QEMU_PACKED AcpiSubHdr;
+
+ struct {
+ uint32_t lapic_addr; /* Local Interrupt Controller Address */
+ uint32_t flags; /* Multiple APIC flags */
+ } QEMU_PACKED *madt;
+ struct {
+ AcpiSubHdr hdr;
+ uint8_t processor_id; /* ACPI Processor ID */
+ uint8_t apic_id; /* APIC ID */
+ uint32_t flags; /* LOcal APIC flags */
+ } QEMU_PACKED *lapic;
+ struct {
+ AcpiSubHdr hdr;
+ uint8_t io_apic_id; /* The I/O APIC's ID */
+ uint8_t reserved; /* constant zero */
+ uint32_t io_apic_addr; /* 32-bit physical address to access */
+ uint32_t gsi_base; /* interrupt inputs start here */
+ } QEMU_PACKED *io_apic;
+ struct {
+ AcpiSubHdr hdr;
+ uint8_t bus; /* constant zero: ISA */
+ uint8_t source; /* this bus-relative interrupt source... */
+ uint32_t gsi; /* ... will signal this global system interrupt */
+ uint16_t flags; /* MPS INTI Flags: Polarity, Trigger Mode */
+ } QEMU_PACKED *int_src_ovr;
+ struct {
+ AcpiSubHdr hdr;
+ uint8_t processor_id; /* ACPI Processor ID */
+ uint16_t flags; /* MPS INTI Flags: Polarity, Trigger Mode */
+ uint8_t lint; /* LAPIC interrupt input for NMI */
+ } QEMU_PACKED *lapic_nmi;
+
+ static const AcpiTableOptions hdrs = {
+ .has_sig = true,
+ .sig = (char *)"APIC",
+ .has_oem_id = true,
+ .oem_id = (char *)"QEMU ",
+ .has_oem_table_id = true,
+ .oem_table_id = (char *)"QEMUMADT"
+ };
+ static const uint8_t pci_isa_irq[] = { 5, 9, 10, 11 };
+
+ unsigned num_lapic, num_int_src_ovr, i;
+ size_t blob_size;
+ char unsigned *blob;
+ Error *err = NULL;
+
+ /* see note on FW_CFG_MAX_CPUS in bochs_bios_init() */
+ num_lapic = pc_apic_id_limit(max_cpus);
+ num_int_src_ovr = sizeof pci_isa_irq + kvm_allows_irq0_override();
+
+ blob_size = (sizeof *madt) * 1 +
+ (sizeof *lapic) * num_lapic +
+ (sizeof *io_apic) * 1 +
+ (sizeof *int_src_ovr) * num_int_src_ovr +
+ (sizeof *lapic_nmi) * 1;
+ blob = g_malloc(blob_size);
+
+ madt = (void *)blob;
+ lapic = (void *)(madt + 1 );
+ io_apic = (void *)(lapic + num_lapic );
+ int_src_ovr = (void *)(io_apic + 1 );
+ lapic_nmi = (void *)(int_src_ovr + num_int_src_ovr);
+
+ madt->lapic_addr = cpu_to_le32(APIC_DEFAULT_ADDRESS);
+ madt->flags = cpu_to_le32(1); /* PCAT_COMPAT */
+
+ /* create a Local APIC structure for each possible APIC ID */
+ for (i = 0; i < num_lapic; ++i) {
+ lapic[i].hdr.type = 0; /* Processor Local APIC */
+ lapic[i].hdr.length = sizeof *lapic;
+ lapic[i].processor_id = i;
+ lapic[i].apic_id = i;
+ lapic[i].flags = cpu_to_le32(0); /* disabled */
+ }
+ /* enable the CPUs with a CPU index in the [0..smp_cpus-1] range */
+ for (i = 0; i < smp_cpus; ++i) {
+ lapic[x86_cpu_apic_id_from_index(i)].flags = cpu_to_le32(1);
+ }
+
+ io_apic->hdr.type = 1; /* I/O APIC */
+ io_apic->hdr.length = sizeof *io_apic;
+ io_apic->io_apic_id = 0;
+ io_apic->reserved = 0;
+ io_apic->io_apic_addr = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
+ io_apic->gsi_base = cpu_to_le32(0);
+
+ for (i = 0; i < sizeof pci_isa_irq; ++i) {
+ int_src_ovr[i].hdr.type = 2; /* Interrupt Source Override */
+ int_src_ovr[i].hdr.length = sizeof *int_src_ovr;
+ int_src_ovr[i].bus = 0;
+ int_src_ovr[i].source = pci_isa_irq[i];
+ int_src_ovr[i].gsi = cpu_to_le32(pci_isa_irq[i]);
+ int_src_ovr[i].flags = cpu_to_le16(0xd);
+ /* active high, level-triggered */
+ }
+ if (kvm_allows_irq0_override()) {
+ int_src_ovr[i].hdr.type = 2; /* Interrupt Source Override */
+ int_src_ovr[i].hdr.length = sizeof *int_src_ovr;
+ int_src_ovr[i].bus = 0;
+ int_src_ovr[i].source = 0;
+ int_src_ovr[i].gsi = cpu_to_le32(2);
+ int_src_ovr[i].flags = cpu_to_le16(0); /* conforms to bus spec */
+ }
+
+ lapic_nmi->hdr.type = 4; /* Local APIC NMI */
+ lapic_nmi->hdr.length = sizeof *lapic_nmi;
+ lapic_nmi->processor_id = 0xff; /* all processors */
+ lapic_nmi->flags = cpu_to_le16(0); /* conforms to bus spec */
+ lapic_nmi->lint = 1; /* NMI connected to LAPIC input LINT1 */
+
+ acpi_table_install(blob, blob_size, false, &hdrs, &err);
+ if (err) {
+ fprintf(stderr, "WARNING: failed to install MADT: %s\n",
+ error_get_pretty(err));
+ error_free(err);
+ }
+ g_free(blob);
+}
+
void pc_acpi_init(const char *default_dsdt)
{
char *filename;
@@ -918,6 +1044,8 @@ void pc_acpi_init(const char *default_dsdt)
g_free(arg);
g_free(filename);
}
+
+ pc_acpi_madt();
}
void *pc_memory_init(MemoryRegion *system_memory,
--
1.7.1
