On 27.03.2013, at 15:00, Alexander Graf wrote: > > On 27.03.2013, at 14:54, Alexander Graf wrote: > >> >> On 27.03.2013, at 14:50, Fabien Chouteau wrote: >> >>> According to the PowePC 750 user's manual, the vector offset for system >> >> PowerPC? >> >>> reset (both /HRESET and /SRESET) is 0x00100. >>> >>> Signed-off-by: Fabien Chouteau <chout...@adacore.com> >>> --- >>> target-ppc/translate_init.c | 8 ++++---- >>> 1 file changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >>> index 781170f..a5bae1e 100644 >>> --- a/target-ppc/translate_init.c >>> +++ b/target-ppc/translate_init.c >>> @@ -2885,7 +2885,7 @@ static void init_excp_7x0 (CPUPPCState *env) >>> env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; >>> env->hreset_excp_prefix = 0x00000000UL; >>> /* Hardware reset vector */ >>> - env->hreset_vector = 0xFFFFFFFCUL; >>> + env->hreset_vector = 0xFFF00100UL; >> >> As you properly explained above, the reset vector is 0x100 according to the >> spec. However, hreset_excp_prefix is 0x0. How do we end up getting to >> 0xfff00100 here? > > According to 7xx_um.pdf (740 / 750 User manual), the IP bit in MSR (bit 25 in > ppc notion) controls whether excp_prefix is 0xfff00000 or 0x00000000. The > spec also says: > > When either HRESET is negated or SRESET transitions to asserted, the > processor attempts to fetch code from the system reset exception vector. The > vector is located at offset 0x00100 from the exception prefix (all zeros or > ones, depending on the setting of the exception prefix bit in the machine > state register (MSR[IP]). The MSR[IP] bit is set for HRESET. > > So on reset, MSR[IP] = 1. That means that hreset_excp_prefix is also wrong > here. > > Please add the respective logic that sets hreset_excp_prefix according to > MSR[IP] on 740 / 750, otherwise whatever you're trying to execute will break > as soon as it gets its first real exception :).
While at it, on exception delivery ILE, ME and IP do not get modified according to the spec. Please verify that we don't accidentally set them to 0 when we deliver an interrupt. Except for machine check interrupts, where MSR.ME = 0. Also, MSR.LE becomes the previous value of MSR.ILE. Not that we'd implement LE mode properly ;). Alex
