On Tue, Nov 03, 2009 at 12:52:10PM +0900, Isaku Yamahata wrote: > On Sun, Nov 01, 2009 at 06:07:30PM +0200, Michael S. Tsirkin wrote: > > On Fri, Oct 30, 2009 at 09:21:11PM +0900, Isaku Yamahata wrote: > > > implemented pci 64bit bar support. > > > The tricky bit is pci_update_mapping(). > > > An OS is allowed to set the BAR such that OS can't address the area > > > pointed by BAR. It doesn't make sense, though. > > > > It might make sense. 32 bit guest can address more than 4G of > > physical RAM, e.g. using PAE. > > Yes, in that case, guest OS will set bar to be under 36 bit. > If PAE were supported, target phys address would be 64 bit. > > > > Since I think qemu can not support this if target phys address is 32 > > bit, we should declare lack of support for 64 bit addressing on these > > platforms, by forcing BAR into 32 bit mode, rather than silently failing > > to map it. > > I don't get your point. And I don't understand the benefit of focing > BAR into 32 bit mode. > Real hardware silently maps BAR to address beyond CPU addressable > area. > Let's stick to PCI spec as you said before. > > 32 bit guest OS will set 64 bit BAR to be smaller 32bit > (or 36bit if PAE). That's it. > Even if 64 bit CPU case, architectally addressable address bit is smaller > than 64 bit. It's CPU implementation dependent. > And guest OS sets BAR according to it. > -- > yamahata
IMO, this is not a question of what guest does or does not do. If qemu is compiled with target phys address size 32 bit, emulated devices can not support a 64 bit BAR. Therefore, according to PCI spec, such devices should declare all BARs as 32 bit. I think you are right that guests on such systems really do not have a way to address PCI devices if BAR is set beyond 4G. But pci emulation is better off not relying on this, IMO. Makes sense? -- MST
