Also tidy the implementation of setcond in order to share code.
Signed-off-by: Richard Henderson <r...@twiddle.net>
---
tcg/aarch64/tcg-target.c | 33 +++++++++++++++++++++++++--------
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index ea1db85..322660d 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -284,6 +284,10 @@ typedef enum {
INSN_LSRV = 0x1ac02400,
INSN_ASRV = 0x1ac02800,
INSN_RORV = 0x1ac02c00,
+
+ /* Conditional select instructions */
+ INSN_CSEL = 0x1a800000,
+ INSN_CSINC = 0x1a800400,
} AArch64Insn;
static inline enum aarch64_ldst_op_data
@@ -435,6 +439,14 @@ static void tcg_fmt_Rdn_limm(TCGContext *s, AArch64Insn
insn, bool ext,
tcg_fmt_Rdn_r_s(s, insn, ext, rd, rn, r, c);
}
+static inline void tcg_fmt_Rdnm_cond(TCGContext *s, AArch64Insn insn,
+ bool ext, TCGReg rd, TCGReg rn,
+ TCGReg rm, TCGCond c)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd
+ | tcg_cond_to_aarch64[c] << 12);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -661,13 +673,6 @@ static void tcg_out_cmp(TCGContext *s, bool ext, TCGReg a,
}
}
-static inline void tcg_out_cset(TCGContext *s, bool ext, TCGReg rd, TCGCond c)
-{
- /* Using CSET alias of CSINC 0x1a800400 Xd, XZR, XZR, invert(cond) */
- unsigned int base = ext ? 0x9a9f07e0 : 0x1a9f07e0;
- tcg_out32(s, base | tcg_cond_to_aarch64[tcg_invert_cond(c)] << 12 | rd);
-}
-
static inline void tcg_out_goto(TCGContext *s, tcg_target_long target)
{
tcg_target_long offset;
@@ -1394,7 +1399,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* FALLTHRU */
case INDEX_op_setcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
- tcg_out_cset(s, 0, a0, args[3]);
+ /* Using CSET alias of CSINC Xd, XZR, XZR, invert(cond) */
+ tcg_fmt_Rdnm_cond(s, INSN_CSINC, 0, a0, TCG_REG_XZR,
+ TCG_REG_XZR, tcg_invert_cond(args[3]));
+ break;
+
+ case INDEX_op_movcond_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_movcond_i64:
+ tcg_out_cmp(s, ext, a1, a2, c2);
+ tcg_fmt_Rdnm_cond(s, INSN_CSEL, ext, a0, REG0(3), REG0(4), args[5]);
break;
case INDEX_op_qemu_ld8u:
@@ -1553,6 +1568,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_brcond_i64, { "r", "rA" } },
{ INDEX_op_setcond_i32, { "r", "r", "rwA" } },
{ INDEX_op_setcond_i64, { "r", "r", "rA" } },
+ { INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } },
+ { INDEX_op_movcond_i64, { "r", "r", "rwA", "rZ", "rZ" } },
{ INDEX_op_qemu_ld8u, { "r", "l" } },
{ INDEX_op_qemu_ld8s, { "r", "l" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 6242136..ff073ca 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -56,7 +56,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
@@ -84,7 +84,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
--
1.8.3.1
