On 15 September 2013 16:31, Michael S. Tsirkin <m...@redhat.com> wrote: > On Sun, Sep 15, 2013 at 04:08:26PM +0100, Peter Maydell wrote: >> The aborts I refer to above are if you misprogram the >> device to try to do a bus master access to some part of >> PCI memory space other than where the host controller's >> BARs are > > So the controller won't claim this transaction. > In that case you are right, they likely > trigger PCI master aborts. > >> (or if you misprogram the controller not to >> map its BARs at all). > > I'm not sure about this one. If BAR is enabled > but part of it maps somewhere outside system RAM, > you likely won't get an error on the PCI bus.
By "not mapping the BAR" I meant "not enabling the BAR". -- PMM
